diff options
| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 00:28:19 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 00:28:19 +0000 |
| commit | 6a45d681e53a99b4c4f63e0b1664626a596a8151 (patch) | |
| tree | 93f2e7b40f4ff7487a536b62da8f6dd2e2531b87 /lib/Target/MSP430/MSP430RegisterInfo.td | |
| parent | 6d37a29588e9a48d81480501f895ac627bf60201 (diff) | |
| download | llvm-6a45d681e53a99b4c4f63e0b1664626a596a8151.tar.gz llvm-6a45d681e53a99b4c4f63e0b1664626a596a8151.tar.bz2 llvm-6a45d681e53a99b4c4f63e0b1664626a596a8151.tar.xz | |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430/MSP430RegisterInfo.td')
| -rw-r--r-- | lib/Target/MSP430/MSP430RegisterInfo.td | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td index f488f00913..f8aec66a7d 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/lib/Target/MSP430/MSP430RegisterInfo.td @@ -43,6 +43,9 @@ def R13B : MSP430Reg<13, "r13">; def R14B : MSP430Reg<14, "r14">; def R15B : MSP430Reg<15, "r15">; +def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; } + +let SubRegIndices = [subreg_8bit] in { def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>; def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>; def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>; @@ -59,13 +62,7 @@ def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>; def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>; def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>; def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>; - -def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; } - -def : SubRegSet<subreg_8bit, [PCW, SPW, SRW, CGW, FPW, R5W, R6W, R7W, - R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], - [PCB, SPB, SRB, CGB, FPB, R5B, R6B, R7B, - R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; +} def GR8 : RegisterClass<"MSP430", [i8], 8, // Volatile registers |