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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 23:28:14 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 23:28:14 +0000 |
commit | f28987b76e758b5f2fcc2c5d2c8e073df54ca91e (patch) | |
tree | 8f60dc5b88bbfc1192d2a780d9a5ee6702535e5f /lib/Target/MSP430/MSP430RegisterInfo.td | |
parent | f14bacc862eb69c7c779858746cc020386ce5590 (diff) | |
download | llvm-f28987b76e758b5f2fcc2c5d2c8e073df54ca91e.tar.gz llvm-f28987b76e758b5f2fcc2c5d2c8e073df54ca91e.tar.bz2 llvm-f28987b76e758b5f2fcc2c5d2c8e073df54ca91e.tar.xz |
Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430/MSP430RegisterInfo.td')
-rw-r--r-- | lib/Target/MSP430/MSP430RegisterInfo.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td index 3ef6ab219d..d1c2e3f791 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/lib/Target/MSP430/MSP430RegisterInfo.td @@ -66,19 +66,19 @@ def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>; def GR8 : RegisterClass<"MSP430", [i8], 8, // Volatile registers - [R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B, + (add R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B, // Frame pointer, sometimes allocable FPB, // Volatile, but not allocable - PCB, SPB, SRB, CGB]>; + PCB, SPB, SRB, CGB)>; def GR16 : RegisterClass<"MSP430", [i16], 16, // Volatile registers - [R12W, R13W, R14W, R15W, R11W, R10W, R9W, R8W, R7W, R6W, R5W, + (add R12W, R13W, R14W, R15W, R11W, R10W, R9W, R8W, R7W, R6W, R5W, // Frame pointer, sometimes allocable FPW, // Volatile, but not allocable - PCW, SPW, SRW, CGW]> + PCW, SPW, SRW, CGW)> { let SubRegClasses = [(GR8 subreg_8bit)]; } |