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| author | Matheus Almeida <matheus.almeida@imgtec.com> | 2013-10-21 12:26:50 +0000 |
|---|---|---|
| committer | Matheus Almeida <matheus.almeida@imgtec.com> | 2013-10-21 12:26:50 +0000 |
| commit | 006cff8d7b60ddf632f8642f01693dace7827d8b (patch) | |
| tree | 9789dabdb04ff17f902100ce5385d30a57334644 /lib/Target/Mips/Disassembler | |
| parent | cebd4010222f28bb68c217047fd0b2c90498f7ca (diff) | |
| download | llvm-006cff8d7b60ddf632f8642f01693dace7827d8b.tar.gz llvm-006cff8d7b60ddf632f8642f01693dace7827d8b.tar.bz2 llvm-006cff8d7b60ddf632f8642f01693dace7827d8b.tar.xz | |
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon
as GAS starts accepting them by name as that would make the assembly easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Disassembler')
| -rw-r--r-- | lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index c8d0d88299..da49564296 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -190,6 +190,11 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, @@ -688,6 +693,18 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + + unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); + Inst.addOperand(MCOperand::CreateReg(Reg)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, |