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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-06 12:28:13 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-09-06 12:28:13 +0000 |
| commit | 99d02d13259620d175986bf9c7e1c07b2640163d (patch) | |
| tree | 8e983fc5e578b7033d786eded79ddb4ecdcda125 /lib/Target/Mips/Disassembler | |
| parent | d31c238372b2ddba147a012f457cae896e6e828f (diff) | |
| download | llvm-99d02d13259620d175986bf9c7e1c07b2640163d.tar.gz llvm-99d02d13259620d175986bf9c7e1c07b2640163d.tar.bz2 llvm-99d02d13259620d175986bf9c7e1c07b2640163d.tar.xz | |
[mips][msa] Made the operand register sets optional for the 2RF format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190143 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Disassembler')
0 files changed, 0 insertions, 0 deletions