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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-13 11:45:36 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-13 11:45:36 +0000 |
| commit | 0e0f907356529765531f27993d7f9cbd15ae6425 (patch) | |
| tree | e4c61a7a7447b3165783fc93132faa040f19875a /lib/Target/Mips/MicroMipsInstrInfo.td | |
| parent | 34b9ca5e145d363361474c21d559077d8c7bdb51 (diff) | |
| download | llvm-0e0f907356529765531f27993d7f9cbd15ae6425.tar.gz llvm-0e0f907356529765531f27993d7f9cbd15ae6425.tar.bz2 llvm-0e0f907356529765531f27993d7f9cbd15ae6425.tar.xz | |
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-3 that was available in MIPS32R2.
To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are tested.
rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.
Depends on D3696
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208690 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MicroMipsInstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/MicroMipsInstrInfo.td | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 54564e2b85..9904bc690c 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -273,8 +273,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM; def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>; def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>; - def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>; - def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>; + def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>, + ISA_MIPS32R2; + def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>, + ISA_MIPS32R2; /// Trap Instructions def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>; |