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author | Reed Kotler <rkotler@mips.com> | 2013-12-08 19:21:47 +0000 |
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committer | Reed Kotler <rkotler@mips.com> | 2013-12-08 19:21:47 +0000 |
commit | 9bdfe3644f5b2d28bb3b368daab6ce78b8a973b8 (patch) | |
tree | bcc7629ae72edf4100e1da52998da1cc0f9fdfdc /lib/Target/Mips/Mips16InstrInfo.cpp | |
parent | c9ea75ee5bcf6a9ced5852b7662f1400a9be8d16 (diff) | |
download | llvm-9bdfe3644f5b2d28bb3b368daab6ce78b8a973b8.tar.gz llvm-9bdfe3644f5b2d28bb3b368daab6ce78b8a973b8.tar.bz2 llvm-9bdfe3644f5b2d28bb3b368daab6ce78b8a973b8.tar.xz |
Make sure we mark these registers as defined. Previously was done
in the td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196731 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips16InstrInfo.cpp')
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.cpp | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp index 05658106bb..4cb9312bcd 100644 --- a/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/lib/Target/Mips/Mips16InstrInfo.cpp @@ -229,9 +229,11 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); if (!NeverUseSaveRestore) { if (isUInt<11>(FrameSize)) - BuildMI(MBB, I, DL, get(Mips::RestoreX16)).addReg(Mips::RA). - addReg(Mips::S0). - addReg(Mips::S1).addReg(Mips::S2).addImm(FrameSize); + BuildMI(MBB, I, DL, get(Mips::RestoreX16)). + addReg(Mips::RA, RegState::Define). + addReg(Mips::S0, RegState::Define). + addReg(Mips::S1, RegState::Define). + addReg(Mips::S2, RegState::Define).addImm(FrameSize); else { int Base = 2040; // should create template function like isUInt that // returns largest possible n bit unsigned integer @@ -240,9 +242,11 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, BuildAddiuSpImm(MBB, I, Remainder); else adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1); - BuildMI(MBB, I, DL, get(Mips::RestoreX16)).addReg(Mips::RA). - addReg(Mips::S0). - addReg(Mips::S1).addReg(Mips::S2).addImm(Base); + BuildMI(MBB, I, DL, get(Mips::RestoreX16)). + addReg(Mips::RA, RegState::Define). + addReg(Mips::S0, RegState::Define). + addReg(Mips::S1, RegState::Define). + addReg(Mips::S2, RegState::Define).addImm(Base); } } else { |