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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-06-21 20:39:10 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-06-21 20:39:10 +0000 |
commit | 54c5bc87992ebeaa9e71f2bfb60ac5cf74b77db3 (patch) | |
tree | 10f8e7a9269390f01b1da8697290bf0aed552476 /lib/Target/Mips/Mips16InstrInfo.td | |
parent | 43d2ff1171d6c9c50ac2b3c5dfaea0746aee99d4 (diff) | |
download | llvm-54c5bc87992ebeaa9e71f2bfb60ac5cf74b77db3.tar.gz llvm-54c5bc87992ebeaa9e71f2bfb60ac5cf74b77db3.tar.bz2 llvm-54c5bc87992ebeaa9e71f2bfb60ac5cf74b77db3.tar.xz |
1. fix null program output after some other changes
2. re-enable null.ll test
3. fix some minor style violations
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158935 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips16InstrInfo.td')
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index fc530939ed..2e0239377d 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -11,19 +11,29 @@ // //===----------------------------------------------------------------------===// +class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { + let Predicates = [InMips16Mode]; +} + +def LI16E : FEXT_RI16<0b01101, (outs CPU16Regs:$rx), + (ins uimm16:$amt), + !strconcat("li", "\t$rx, $amt"), + [(set CPU16Regs:$rx, immZExt16:$amt )],IILoad>; + let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1, isBarrier=1, hasCtrlDep=1, rx=0, nd=0, l=0, ra=0 in -def RET16 : FRR16_JALRC < (outs), (ins CPURAReg:$target), - "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>; +def RET16 : FRR16_JALRC + < (outs), (ins CPURAReg:$target), + "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>; // As stack alignment is always done with addiu, we need a 16-bit immediate let Defs = [SP], Uses = [SP] in { def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt), - "!ADJCALLSTACKDOWN $amt", - [(callseq_start timm:$amt)]>; + "!ADJCALLSTACKDOWN $amt", + [(callseq_start timm:$amt)]>; def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2), - "!ADJCALLSTACKUP $amt1", - [(callseq_end timm:$amt1, timm:$amt2)]>; + "!ADJCALLSTACKUP $amt1", + [(callseq_end timm:$amt1, timm:$amt2)]>; } @@ -31,4 +41,7 @@ def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2), let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in def JumpLinkReg16: FRR16_JALRC<(outs), (ins CPU16Regs:$rs, variable_ops), - "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; + "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; + +// Small immediates +def : Mips16Pat<(i32 immZExt16:$in), (LI16E immZExt16:$in)>; |