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author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-01-21 15:21:14 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-01-21 15:21:14 +0000 |
commit | f862a4aefe2b50bc7643d27ae6689356cb977f63 (patch) | |
tree | ef6ff9f5e3db3e973b877d35b0bb895b88e5dfeb /lib/Target/Mips/Mips16InstrInfo.td | |
parent | 2b9c11c071611566240fa0d36aefbd324cec4058 (diff) | |
download | llvm-f862a4aefe2b50bc7643d27ae6689356cb977f63.tar.gz llvm-f862a4aefe2b50bc7643d27ae6689356cb977f63.tar.bz2 llvm-f862a4aefe2b50bc7643d27ae6689356cb977f63.tar.xz |
[mips][sched] Split IILoad into II_L[BHWD], II_L[BHW]U, II_L[WD][LR], and II_RESTORE
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199749 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips16InstrInfo.td')
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 8d8b2ed20b..b604b69bd4 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -787,7 +787,7 @@ def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { // Purpose: Load Byte (Extended) // To load a byte from memory as a signed value. // -def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{ +def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, II_LB>, MayLoad{ let isCodeGenOnly = 1; } @@ -797,7 +797,7 @@ def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{ // To load a byte from memory as a unsigned value. // def LbuRxRyOffMemX16: - FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad { + FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, II_LBU>, MayLoad { let isCodeGenOnly = 1; } @@ -806,7 +806,7 @@ def LbuRxRyOffMemX16: // Purpose: Load Halfword signed (Extended) // To load a halfword from memory as a signed value. // -def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{ +def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, II_LH>, MayLoad{ let isCodeGenOnly = 1; } @@ -816,7 +816,7 @@ def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{ // To load a halfword from memory as an unsigned value. // def LhuRxRyOffMemX16: - FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad { + FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, II_LHU>, MayLoad { let isCodeGenOnly = 1; } @@ -843,7 +843,7 @@ def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> { // Purpose: Load Word (Extended) // To load a word from memory as a signed value. // -def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{ +def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, II_LW>, MayLoad{ let isCodeGenOnly = 1; } @@ -851,13 +851,13 @@ def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{ // Purpose: Load Word (SP-Relative, Extended) // To load an SP-relative word from memory as a signed value. // -def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10010, "lw", IILoad>, MayLoad{ +def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10010, "lw", II_LW>, MayLoad{ let Uses = [SP]; } -def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad; +def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad; -def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad; +def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad; // // Format: MOVE r32, rz MIPS16e // Purpose: Move @@ -961,7 +961,7 @@ def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; def Restore16: FI8_SVRS16<0b1, (outs), (ins variable_ops), - "", [], IILoad >, MayLoad { + "", [], II_RESTORE >, MayLoad { let isCodeGenOnly = 1; let Defs = [SP]; let Uses = [SP]; @@ -970,7 +970,7 @@ def Restore16: def RestoreX16: FI8_SVRS16<0b1, (outs), (ins variable_ops), - "", [], IILoad >, MayLoad { + "", [], II_RESTORE >, MayLoad { let isCodeGenOnly = 1; let Defs = [SP]; let Uses = [SP]; |