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| author | Reed Kotler <rkotler@mips.com> | 2013-02-21 04:22:38 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2013-02-21 04:22:38 +0000 |
| commit | ffbe432595c78ba28c8a9d200bf92996eed5e5d9 (patch) | |
| tree | e8e487c8bd384da748598efd81d144d945c1e047 /lib/Target/Mips/Mips16InstrInfo.td | |
| parent | b8ebc9e2444c73126bdc812165f808f22af10cfa (diff) | |
| download | llvm-ffbe432595c78ba28c8a9d200bf92996eed5e5d9.tar.gz llvm-ffbe432595c78ba28c8a9d200bf92996eed5e5d9.tar.bz2 llvm-ffbe432595c78ba28c8a9d200bf92996eed5e5d9.tar.xz | |
Expand the sel pseudo/macro. This generates basic blocks where previously
there were inline br .+4 instructions. Soon everything can enjoy the
full instruction scheduling experience.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175718 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips16InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 1cb4a0edfd..9e07b95cc6 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -76,6 +76,10 @@ class F2RI16_ins<bits<5> _op, string asmstr, let Constraints = "$rx_ = $rx"; } +class FRI16_B_ins<bits<5> _op, string asmstr, + InstrItinClass itin>: + FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), + !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>; // // Compare a register and immediate and place result in CC // Implicit use of T8 @@ -362,6 +366,7 @@ class Sel<string op>: !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> { //let isCodeGenOnly=1; let Constraints = "$rd = $rd_"; + let usesCustomInserter = 1; } // @@ -520,6 +525,14 @@ def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; // // Format: BEQZ rx, offset MIPS16e +// Purpose: Branch on Equal to Zero +// To test a GPR then do a PC-relative conditional branch. +// +def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; + + +// +// Format: BEQZ rx, offset MIPS16e // Purpose: Branch on Equal to Zero (Extended) // To test a GPR then do a PC-relative conditional branch. // @@ -533,6 +546,13 @@ def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; // // Format: BNEZ rx, offset MIPS16e +// Purpose: Branch on Not Equal to Zero +// To test a GPR then do a PC-relative conditional branch. +// +def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; + +// +// Format: BNEZ rx, offset MIPS16e // Purpose: Branch on Not Equal to Zero (Extended) // To test a GPR then do a PC-relative conditional branch. // |