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author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 13:13:03 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 13:13:03 +0000 |
commit | af0d72a6f9ef752ad871e53304d22fb5c930adb9 (patch) | |
tree | 5d9948200c53be92c0c669d543abf36d5e136c4b /lib/Target/Mips/Mips32r6InstrFormats.td | |
parent | 438c85b50edfff10fa2991ee3a01172b018a46af (diff) | |
download | llvm-af0d72a6f9ef752ad871e53304d22fb5c930adb9.tar.gz llvm-af0d72a6f9ef752ad871e53304d22fb5c930adb9.tar.bz2 llvm-af0d72a6f9ef752ad871e53304d22fb5c930adb9.tar.xz |
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.
Summary:
The linked-load, store-conditional operations have been re-encoded such
that have a 9-bit offset instead of the 16-bit offset they have prior to
MIPS32r6/MIPS64r6.
While implementing this, I noticed that the atomic load/store pseudos always
emit a sign extension using sll and sra. I have improved this to use seb/seh
when they are available (MIPS32r2/MIPS64r2 and above).
Depends on D4118
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211018 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips32r6InstrFormats.td')
-rw-r--r-- | lib/Target/Mips/Mips32r6InstrFormats.td | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips32r6InstrFormats.td b/lib/Target/Mips/Mips32r6InstrFormats.td index 6eb8c4650c..697d550615 100644 --- a/lib/Target/Mips/Mips32r6InstrFormats.td +++ b/lib/Target/Mips/Mips32r6InstrFormats.td @@ -39,6 +39,7 @@ def OPGROUP_DAUI : OPGROUP<0b011101>; def OPGROUP_PCREL : OPGROUP<0b111011>; def OPGROUP_REGIMM : OPGROUP<0b000001>; def OPGROUP_SPECIAL : OPGROUP<0b000000>; +// The spec occasionally names this value LL, LLD, SC, or SCD. def OPGROUP_SPECIAL3 : OPGROUP<0b011111>; // The spec names this constant LWC2, LDC2, SWC2, and SDC2 in different places. def OPGROUP_COP2LDST : OPGROUP<0b010010>; @@ -84,6 +85,12 @@ def OPCODE6_DBITSWAP : OPCODE6<0b100100>; def OPCODE6_JALR : OPCODE6<0b001001>; def OPCODE6_CACHE : OPCODE6<0b100101>; def OPCODE6_PREF : OPCODE6<0b110101>; +// The next four constants are unnamed in the spec. These names are taken from +// the OPGROUP names they are used with. +def OPCODE6_LL : OPCODE6<0b110110>; +def OPCODE6_LLD : OPCODE6<0b110111>; +def OPCODE6_SC : OPCODE6<0b100110>; +def OPCODE6_SCD : OPCODE6<0b100111>; class FIELD_FMT<bits<5> Val> { bits<5> Value = Val; @@ -411,6 +418,23 @@ class SPECIAL3_DALIGN_FM<OPCODE6 Operation> : MipsR6Inst { let Inst{5-0} = Operation.Value; } +class SPECIAL3_LL_SC_FM<OPCODE6 Operation> : MipsR6Inst { + bits<5> rt; + bits<21> addr; + bits<5> base = addr{20-16}; + bits<9> offset = addr{8-0}; + + bits<32> Inst; + + let Inst{31-26} = OPGROUP_SPECIAL3.Value; + let Inst{25-21} = base; + let Inst{20-16} = rt; + let Inst{15-7} = offset; + let Inst{5-0} = Operation.Value; + + string DecoderMethod = "DecodeSpecial3LlSc"; +} + class REGIMM_FM<OPCODE5 Operation> : MipsR6Inst { bits<5> rs; bits<16> imm; |