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authorAkira Hatanaka <ahatanaka@mips.com>2011-12-07 23:31:26 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2011-12-07 23:31:26 +0000
commit08a7d92da6f6fcd5879d1c8a7ab69b23e33831cb (patch)
tree216f9d1dc52ba137a169d5c379cbf53e6f90bd3e /lib/Target/Mips/Mips64InstrInfo.td
parentf99c1e5a1954dbaece9ceb137ec8aa4dfeb33050 (diff)
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Modify class ReadHardware and add definition of 64-bit version of instruction
RDHWR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146101 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
-rw-r--r--lib/Target/Mips/Mips64InstrInfo.td2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 301905b036..d87528ad5f 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -219,6 +219,8 @@ let Uses = [SP_64] in
def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
Requires<[IsN64]>;
+def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
+
def DEXT : ExtBase<3, "dext", CPU64Regs>;
def DINS : InsBase<7, "dins", CPU64Regs>;