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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-10-17 18:17:58 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-10-17 18:17:58 +0000 |
| commit | 2d0a61da62b19d9597d569fb99082b418e214a12 (patch) | |
| tree | 98b32992873232be85adeafb8d4b8eab5d2d77cf /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | e9e579155614654665ef7a4e3aa5c7a8d4a49f01 (diff) | |
| download | llvm-2d0a61da62b19d9597d569fb99082b418e214a12.tar.gz llvm-2d0a61da62b19d9597d569fb99082b418e214a12.tar.bz2 llvm-2d0a61da62b19d9597d569fb99082b418e214a12.tar.xz | |
Add definition of a base class for logical shift/rotate instructions with two
source registers and redefine 32-bit and 64-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142210 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 4686699f9c..29cc76ce44 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -51,14 +51,6 @@ class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm, shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt_64, CPU64Regs>; -class LogicR_shift_rotate_reg64<bits<6> func, bits<5> _shamt, string instr_asm, - SDNode OpNode>: - FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$c, CPU64Regs:$b), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu> { - let shamt = _shamt; -} - // Mul, Div let Defs = [HI64, LO64] in { let isCommutable = 1 in @@ -124,15 +116,15 @@ def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>; def DSLL32 : shift_rotate_imm64_32<0x3c, 0x00, "dsll32", shl>; def DSRL32 : shift_rotate_imm64_32<0x3e, 0x00, "dsrl32", srl>; def DSRA32 : shift_rotate_imm64_32<0x3f, 0x00, "dsra32", sra>; -def DSLLV : LogicR_shift_rotate_reg64<0x24, 0x00, "dsllv", shl>; -def DSRLV : LogicR_shift_rotate_reg64<0x26, 0x00, "dsrlv", srl>; -def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>; +def DSLLV : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>; +def DSRLV : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>; +def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>; // Rotate Instructions let Predicates = [HasMips64r2] in { def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>; def DROTR32 : shift_rotate_imm64_32<0x3e, 0x01, "drotr32", rotr>; - def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>; + def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>; } /// Load and Store Instructions |