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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-10-12 01:05:13 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-10-12 01:05:13 +0000 |
| commit | 41f9a430cbb47b1d6172a91d2a70adc552b65678 (patch) | |
| tree | 2726936482d3effddbb3b4d031d1326f6cd01c52 /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 6baabc1dd06f0d469900d7d5a6f8e724e5aa3f5a (diff) | |
| download | llvm-41f9a430cbb47b1d6172a91d2a70adc552b65678.tar.gz llvm-41f9a430cbb47b1d6172a91d2a70adc552b65678.tar.bz2 llvm-41f9a430cbb47b1d6172a91d2a70adc552b65678.tar.xz | |
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141761 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index f38ddc2d92..49b0223643 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -36,14 +36,6 @@ def imm32_63 : ImmLeaf<i64, //===----------------------------------------------------------------------===// // Instructions specific format //===----------------------------------------------------------------------===// - -// Logical -let isCommutable = 1 in -class LogicNOR64<bits<6> op, bits<6> func, string instr_asm>: - FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPU64Regs:$dst, (not (or CPU64Regs:$b, CPU64Regs:$c)))], IIAlu>; - // Shifts class LogicR_shift_rotate_imm64<bits<6> func, bits<5> _rs, string instr_asm, SDNode OpNode, PatFrag PF>: @@ -118,7 +110,7 @@ def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>; def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>; def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>; -def NOR64 : LogicNOR64<0x00, 0x27, "nor">; +def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; /// Shift Instructions def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>; |