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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-10-17 18:01:00 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-10-17 18:01:00 +0000 |
| commit | a01820a50824bf592d0a2900cf17ae3adfd5575a (patch) | |
| tree | 828dac2c8557d372d932cccfabb6dc5469c85921 /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 9904056a7061f6e42d38dd565c23990f0a56e9e1 (diff) | |
| download | llvm-a01820a50824bf592d0a2900cf17ae3adfd5575a.tar.gz llvm-a01820a50824bf592d0a2900cf17ae3adfd5575a.tar.bz2 llvm-a01820a50824bf592d0a2900cf17ae3adfd5575a.tar.xz | |
Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142205 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 49b0223643..7d55cce9fa 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -28,6 +28,9 @@ def Subtract32 : SDNodeXForm<imm, [{ return getI32Imm((unsigned)N->getZExtValue() - 32); }]>; +// shamt field must fit in 5 bits. +def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>; + // imm32_63 predicate - True if imm is in range [32, 63]. def imm32_63 : ImmLeaf<i64, [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}], @@ -113,9 +116,9 @@ def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>; def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; /// Shift Instructions -def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>; -def DSRL : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5>; -def DSRA : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5>; +def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5_64>; +def DSRL : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5_64>; +def DSRA : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5_64>; def DSLL32 : LogicR_shift_rotate_imm64<0x3c, 0x00, "dsll32", shl, imm32_63>; def DSRL32 : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>; def DSRA32 : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>; @@ -125,7 +128,8 @@ def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>; // Rotate Instructions let Predicates = [HasMips64r2] in { - def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, immZExt5>; + def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, + immZExt5_64>; def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr, imm32_63>; def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>; |