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authorAkira Hatanaka <ahatanaka@mips.com>2011-09-30 17:26:36 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2011-09-30 17:26:36 +0000
commita64556ffda503a416b2594104f8f82345734b4d9 (patch)
treea95454e9f01a6fe25c34a9690328a493d74224f3 /lib/Target/Mips/Mips64InstrInfo.td
parent98602ac9a99c5243a9e1abdb0e72dd326ec4958d (diff)
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isCommutable should be 0 for DSUBu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140862 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
-rw-r--r--lib/Target/Mips/Mips64InstrInfo.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index d28aff0813..c500c1a8fe 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -102,7 +102,7 @@ def DXORi : LogicI64<0x0e, "xori", xor>;
/// Arithmetic Instructions (3-Operand, R-Type)
def DADDu : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
-def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu, 1>;
+def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu>;
def DAND : LogicR64<0x24, "and", and>;
def DOR : LogicR64<0x25, "or", or>;
def DXOR : LogicR64<0x26, "xor", xor>;