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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 03:48:24 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 03:48:24 +0000 |
| commit | cdc0c59d1ed5ac6c616b8899222d1e102ccd9f8d (patch) | |
| tree | 5ae6b951369743d61bb912a2b66cc2b65ea5414f /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 0dad34a9bf850132e9ec84397f13604143c3aeff (diff) | |
| download | llvm-cdc0c59d1ed5ac6c616b8899222d1e102ccd9f8d.tar.gz llvm-cdc0c59d1ed5ac6c616b8899222d1e102ccd9f8d.tar.bz2 llvm-cdc0c59d1ed5ac6c616b8899222d1e102ccd9f8d.tar.xz | |
[mips] Refactor shift instructions with register operands. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170650 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 13674a41a1..c57c3499f6 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -110,9 +110,9 @@ def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; def DSLL : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>; def DSRL : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>; def DSRA : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>; -def DSLLV : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>; -def DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>; -def DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>; +def DSLLV : shift_rotate_reg<"dsllv", shl, CPU64Regs>, SRLV_FM<0x14, 0>; +def DSRLV : shift_rotate_reg<"dsrlv", srl, CPU64Regs>, SRLV_FM<0x16, 0>; +def DSRAV : shift_rotate_reg<"dsrav", sra, CPU64Regs>, SRLV_FM<0x17, 0>; def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>; def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>; def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>; @@ -121,7 +121,7 @@ def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>; let Predicates = [HasMips64r2, HasStdEnc], DecoderNamespace = "Mips64" in { def DROTR : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>; - def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>; + def DROTRV : shift_rotate_reg<"drotrv", rotr, CPU64Regs>, SRLV_FM<0x16, 1>; } let DecoderNamespace = "Mips64" in { |