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authorAkira Hatanaka <ahatanaka@mips.com>2011-10-03 21:06:13 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2011-10-03 21:06:13 +0000
commitdda4a07cd818fdfe2b49412e32e0e12d9e566e31 (patch)
tree59d9f1b80a2e26173247c054871f5de39415e573 /lib/Target/Mips/Mips64InstrInfo.td
parent0e6a24d92ab4661bb39f838ac390ccb17f649cb5 (diff)
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Add support for 64-bit divide instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
-rw-r--r--lib/Target/Mips/Mips64InstrInfo.td7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 2fdc2ff007..60fc40ca61 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -96,6 +96,11 @@ let Defs = [HI64, LO64] in {
class Mul64<bits<6> func, string instr_asm, InstrItinClass itin>:
FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
!strconcat(instr_asm, "\t$a, $b"), [], itin>;
+
+ class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
+ FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
+ !strconcat(instr_asm, "\t$$zero, $a, $b"),
+ [(op CPU64Regs:$a, CPU64Regs:$b)], itin>;
}
// Move from Hi/Lo
@@ -150,6 +155,8 @@ let Predicates = [HasMips64r2] in {
/// Multiply and Divide Instructions.
def DMULT : Mul64<0x1c, "dmult", IIImul>;
def DMULTu : Mul64<0x1d, "dmultu", IIImul>;
+def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
+def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
let Defs = [HI64] in
def MTHI64 : MoveToLOHI64<0x11, "mthi">;