diff options
| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-15 12:18:23 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-15 12:18:23 +0000 |
| commit | 9f6a386e6a7a8931f824a95f995e76ce32de2e30 (patch) | |
| tree | 62df5c5a54b155a67e49e70b5674f91413c276fe /lib/Target/Mips/Mips64r6InstrInfo.td | |
| parent | b7ba5c2e2e9d8d381ea759c6d5dd43eba631006d (diff) | |
| download | llvm-9f6a386e6a7a8931f824a95f995e76ce32de2e30.tar.gz llvm-9f6a386e6a7a8931f824a95f995e76ce32de2e30.tar.bz2 llvm-9f6a386e6a7a8931f824a95f995e76ce32de2e30.tar.xz | |
[mips][mips64r6] Add bitswap, and dbitswap
Summary: Depends on D3728
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208877 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64r6InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64r6InstrInfo.td | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td index bc970436f0..0f48784898 100644 --- a/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/lib/Target/Mips/Mips64r6InstrInfo.td @@ -29,6 +29,7 @@ class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>; class DAUI_ENC : DAUI_FM; class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>; class DATI_ENC : REGIMM_FM<OPCODE5_DATI>; +class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>; class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>; class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>; class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>; @@ -48,6 +49,7 @@ class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>; class DAHI_DESC : AUI_DESC_BASE<"dahi", GPR64Opnd>; class DATI_DESC : AUI_DESC_BASE<"dati", GPR64Opnd>; class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>; +class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>; class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd>; class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd>; class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd>; @@ -67,7 +69,7 @@ def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6; def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6; def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6; def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6; -def DBITSWAP; +def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6; def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6; // def DLSA; // See MSA |