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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-27 02:11:20 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-27 02:11:20 +0000 |
commit | 2df483efb3a3d99dd82eb88e13490ae464bf0e43 (patch) | |
tree | b4c3a7a1329fa077d0b05e3e53ec62714866c9ec /lib/Target/Mips/MipsDSPInstrFormats.td | |
parent | fd89e6ffdab95ae6b4568b8a4153064952f61ea6 (diff) | |
download | llvm-2df483efb3a3d99dd82eb88e13490ae464bf0e43.tar.gz llvm-2df483efb3a3d99dd82eb88e13490ae464bf0e43.tar.bz2 llvm-2df483efb3a3d99dd82eb88e13490ae464bf0e43.tar.xz |
MIPS DSP: all the remaining instructions which read or write accumulators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsDSPInstrFormats.td')
-rw-r--r-- | lib/Target/Mips/MipsDSPInstrFormats.td | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsDSPInstrFormats.td b/lib/Target/Mips/MipsDSPInstrFormats.td index f57c55a557..2a0bc2eaae 100644 --- a/lib/Target/Mips/MipsDSPInstrFormats.td +++ b/lib/Target/Mips/MipsDSPInstrFormats.td @@ -24,6 +24,43 @@ class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { let Predicates = [HasDSP]; } +class PseudoDSP<dag outs, dag ins, list<dag> pattern>: + MipsPseudo<outs, ins, "", pattern> { + let Predicates = [HasDSP]; +} + +// DPA.W.PH sub-class format. +class DPA_W_PH_FMT<bits<5> op> : DSPInst { + bits<2> ac; + bits<5> rs; + bits<5> rt; + + let Opcode = SPECIAL3_OPCODE.V; + + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-13} = 0; + let Inst{12-11} = ac; + let Inst{10-6} = op; + let Inst{5-0} = 0b110000; +} + +// MULT sub-class format. +class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst { + bits<2> ac; + bits<5> rs; + bits<5> rt; + + let Opcode = opcode; + + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-13} = 0; + let Inst{12-11} = ac; + let Inst{10-6} = 0; + let Inst{5-0} = funct; +} + // EXTR.W sub-class format (type 1). class EXTR_W_TY1_FMT<bits<5> op> : DSPInst { bits<5> rt; @@ -39,3 +76,30 @@ class EXTR_W_TY1_FMT<bits<5> op> : DSPInst { let Inst{10-6} = op; let Inst{5-0} = 0b111000; } + +// SHILO sub-class format. +class SHILO_R1_FMT<bits<5> op> : DSPInst { + bits<2> ac; + bits<6> shift; + + let Opcode = SPECIAL3_OPCODE.V; + + let Inst{25-20} = shift; + let Inst{19-13} = 0; + let Inst{12-11} = ac; + let Inst{10-6} = op; + let Inst{5-0} = 0b111000; +} + +class SHILO_R2_FMT<bits<5> op> : DSPInst { + bits<2> ac; + bits<5> rs; + + let Opcode = SPECIAL3_OPCODE.V; + + let Inst{25-21} = rs; + let Inst{20-13} = 0; + let Inst{12-11} = ac; + let Inst{10-6} = op; + let Inst{5-0} = 0b111000; +} |