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| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-07-30 10:12:14 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-07-30 10:12:14 +0000 |
| commit | b67775df0cc702cd94408200ff2d58cf83f1334a (patch) | |
| tree | ff1c5874d7360f835387f75ee801346b235ab851 /lib/Target/Mips/MipsInstrFPU.td | |
| parent | d6a721b14d94791458d6f4d80832d3f3b9e9cd11 (diff) | |
| download | llvm-b67775df0cc702cd94408200ff2d58cf83f1334a.tar.gz llvm-b67775df0cc702cd94408200ff2d58cf83f1334a.tar.bz2 llvm-b67775df0cc702cd94408200ff2d58cf83f1334a.tar.xz | |
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrFPU.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index ce68a28dfc..c73070bf34 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -189,9 +189,9 @@ class SWXC1_FT<string opstr, RegisterOperand DRC, RegisterOperand PRC, class BC1F_FT<string opstr, InstrItinClass Itin, SDPatternOperator Op = null_frag> : - InstSE<(outs), (ins FCC:$fcc, brtarget:$offset), + InstSE<(outs), (ins FCCRegsOpnd:$fcc, brtarget:$offset), !strconcat(opstr, "\t$fcc, $offset"), - [(MipsFPBrcond Op, FCC:$fcc, bb:$offset)], Itin, FrmFI> { + [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, FrmFI> { let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; |