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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-10-11 18:49:17 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-10-11 18:49:17 +0000 |
| commit | 3e3427a5c3fe8303723129207ce1864bee8fa481 (patch) | |
| tree | 9af5a422f22d85e558706d5ddc673ff80be51609 /lib/Target/Mips/MipsInstrFormats.td | |
| parent | 2e350479478ccf809e2142a4f0ad8062342577cc (diff) | |
| download | llvm-3e3427a5c3fe8303723129207ce1864bee8fa481.tar.gz llvm-3e3427a5c3fe8303723129207ce1864bee8fa481.tar.bz2 llvm-3e3427a5c3fe8303723129207ce1864bee8fa481.tar.xz | |
Add support for conditional branch instructions with 64-bit register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141694 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrFormats.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index 9ef75a1a13..d246a26eb2 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -90,6 +90,21 @@ class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, let Inst{15-0} = imm16; } +class CBranchBase<bits<6> op, dag outs, dag ins, string asmstr, + list<dag> pattern, InstrItinClass itin>: + MipsInst<outs, ins, asmstr, pattern, itin> +{ + bits<5> rs; + bits<5> rt; + bits<16> imm16; + + let opcode = op; + + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-0} = imm16; +} + //===----------------------------------------------------------------------===// // Format J instruction class in Mips : <|opcode|address|> //===----------------------------------------------------------------------===// |