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| author | Akira Hatanaka <ahatanak@gmail.com> | 2011-04-15 21:00:26 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-04-15 21:00:26 +0000 |
| commit | 0bf3dfbef60e36827df9c7e12b62503f1e345cd0 (patch) | |
| tree | 2d216dbfb7ecf59bc8c895297ca198d605f6f844 /lib/Target/Mips/MipsInstrInfo.cpp | |
| parent | b485de5d8c3fe0c62c0b07f63f64bd10f6803c17 (diff) | |
| download | llvm-0bf3dfbef60e36827df9c7e12b62503f1e345cd0.tar.gz llvm-0bf3dfbef60e36827df9c7e12b62503f1e345cd0.tar.bz2 llvm-0bf3dfbef60e36827df9c7e12b62503f1e345cd0.tar.xz | |
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.cpp | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index be044fa1f3..d4401a1f6e 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -1,15 +1,15 @@ -//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===// +//===- MipsInstrInfo.cpp - Mips Instruction Information --------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // // This file contains the Mips implementation of the TargetInstrInfo class. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// #include "MipsInstrInfo.h" #include "MipsTargetMachine.h" @@ -161,10 +161,10 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, if (RC == Mips::CPURegsRegisterClass) BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill)) - .addImm(0).addFrameIndex(FI); + .addImm(0).addFrameIndex(FI); else if (RC == Mips::FGR32RegisterClass) - BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill)) - .addImm(0).addFrameIndex(FI); + BuildMI(MBB, I, DL, get(Mips::SWC1)) + .addReg(SrcReg, getKillRegState(isKill)).addImm(0).addFrameIndex(FI); else if (RC == Mips::AFGR64RegisterClass) { if (!TM.getSubtarget<MipsSubtarget>().isMips1()) { BuildMI(MBB, I, DL, get(Mips::SDC1)) @@ -200,7 +200,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI); else if (RC == Mips::AFGR64RegisterClass) { if (!TM.getSubtarget<MipsSubtarget>().isMips1()) { - BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI); + BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg) + .addImm(0).addFrameIndex(FI); } else { const TargetRegisterInfo *TRI = MBB.getParent()->getTarget().getRegisterInfo(); @@ -214,9 +215,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, llvm_unreachable("Register class not handled!"); } -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Branch Analysis -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// static unsigned GetAnalyzableBrOpc(unsigned Opc) { return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || |