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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-10-15 01:21:37 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-10-15 01:21:37 +0000 |
| commit | 397f6da28cc889597e8c267e15154f1f70a0922a (patch) | |
| tree | fbe46d4bbd84f85ba67131c955c50deba3c24482 /lib/Target/Mips/MipsInstrInfo.td | |
| parent | adb1297d49dd345821d7aa91057a0b22e6209a16 (diff) | |
| download | llvm-397f6da28cc889597e8c267e15154f1f70a0922a.tar.gz llvm-397f6da28cc889597e8c267e15154f1f70a0922a.tar.bz2 llvm-397f6da28cc889597e8c267e15154f1f70a0922a.tar.xz | |
[mips] Use predicates to guard instructions using accumulator registers instead
of relying on AddedComplexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192665 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 6e06ba21c6..842aab08d0 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1030,21 +1030,13 @@ def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x18>; def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x19>; -def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>; -def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>; def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>; def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>; -def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv, - 0, 1, 1>; -def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv, - 0, 1, 1>; def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>; def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>; -def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>; -def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>; /// Sign Ext In Register Instructions. def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; @@ -1071,10 +1063,22 @@ def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>; def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>; def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>; + +let Predicates = [HasStdEnc, NotDSP] in { +def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>; +def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>; +def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>; +def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>; def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; +} + +def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv, + 0, 1, 1>; +def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv, + 0, 1, 1>; def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; |