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| author | Akira Hatanaka <ahatanak@gmail.com> | 2011-09-20 23:53:09 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-09-20 23:53:09 +0000 |
| commit | 56633441271106376b39a47bbe5b59f85144b64d (patch) | |
| tree | f8fa336fe8f20d293a9d5ef60b96c522c22caf84 /lib/Target/Mips/MipsInstrInfo.td | |
| parent | 4d1d86bac9dbee62819b4a276fcfe01a6b004d39 (diff) | |
| download | llvm-56633441271106376b39a47bbe5b59f85144b64d.tar.gz llvm-56633441271106376b39a47bbe5b59f85144b64d.tar.bz2 llvm-56633441271106376b39a47bbe5b59f85144b64d.tar.xz | |
Change the names of functions isMips* to hasMips*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140214 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index d4c624fe04..5890a4f29a 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -125,8 +125,8 @@ def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">; def HasBitCount : Predicate<"Subtarget.hasBitCount()">; def HasSwap : Predicate<"Subtarget.hasSwap()">; def HasCondMov : Predicate<"Subtarget.hasCondMov()">; -def IsMips32 : Predicate<"Subtarget.isMips32()">; -def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">; +def HasMips32 : Predicate<"Subtarget.hasMips32()">; +def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">; //===----------------------------------------------------------------------===// // Mips Operand, Complex Patterns and Transformations Definitions. @@ -409,7 +409,7 @@ class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src), class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins, list<dag> pattern, InstrItinClass itin>: FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), - pattern, itin>, Requires<[IsMips32r2]> { + pattern, itin>, Requires<[HasMips32r2]> { bits<5> pos; bits<5> sz; let rd = sz; @@ -546,7 +546,7 @@ def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>; def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>; // Rotate Instructions -let Predicates = [IsMips32r2] in { +let Predicates = [HasMips32r2] in { def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>; def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>; } @@ -683,7 +683,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>; // MUL is a assembly macro in the current used ISAs. In recent ISA's // it is a real instruction. -def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[IsMips32]>; +def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[HasMips32]>; def RDHWR : ReadHardware; |