diff options
author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-10-01 09:48:56 +0000 |
---|---|---|
committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-10-01 09:48:56 +0000 |
commit | d59ad8a8013fd76177fb61c741562af3024d34cd (patch) | |
tree | f9eee7577972b76ae2852a606fe1a453f5648537 /lib/Target/Mips/MipsInstrInfo.td | |
parent | c8d0d007811731b114fc0300cd2a1c18258366b0 (diff) | |
download | llvm-d59ad8a8013fd76177fb61c741562af3024d34cd.tar.gz llvm-d59ad8a8013fd76177fb61c741562af3024d34cd.tar.bz2 llvm-d59ad8a8013fd76177fb61c741562af3024d34cd.tar.xz |
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191734 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 1f802891f3..f92f3336f1 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -282,11 +282,22 @@ def MipsMemAsmOperand : AsmOperandClass { let ParserMethod = "parseMemOperand"; } +def MipsInvertedImmoperand : AsmOperandClass { + let Name = "InvNum"; + let RenderMethod = "addImmOperands"; + let ParserMethod = "parseInvNum"; +} + def PtrRegAsmOperand : AsmOperandClass { let Name = "PtrReg"; let ParserMethod = "parsePtrReg"; } + +def InvertedImOperand : Operand<i32> { + let ParserMatchClass = MipsInvertedImmoperand; +} + // Address operand def mem : Operand<iPTR> { let PrintMethod = "printMemOperand"; @@ -1120,6 +1131,11 @@ def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : InstAlias<"sub, $rd, $rs, $imm", + (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>; +def : InstAlias<"subu, $rd, $rs, $imm", + (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>; + //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// @@ -1139,8 +1155,6 @@ class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : !strconcat(instr_asm, "\t$rt, $imm32")> ; def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>; - - //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// |