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| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-08-26 10:02:40 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-08-26 10:02:40 +0000 |
| commit | e4bf77a1282bfdacb61bae192fdf79a696be780a (patch) | |
| tree | f4b82b0b4848abc3baf80cf4ad555610395d7119 /lib/Target/Mips/MipsInstrInfo.td | |
| parent | 4989188a40c4e9cd1016584960296d795e252a6c (diff) | |
| download | llvm-e4bf77a1282bfdacb61bae192fdf79a696be780a.tar.gz llvm-e4bf77a1282bfdacb61bae192fdf79a696be780a.tar.bz2 llvm-e4bf77a1282bfdacb61bae192fdf79a696be780a.tar.xz | |
This patch implements trap instructions for mips. The test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189213 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 3c90e756ef..94f9ee6f95 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -630,6 +630,9 @@ class TEQ_FT<string opstr, RegisterOperand RO> : InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>; +class TEQI_FT<string opstr, RegisterOperand RO> : + InstSE<(outs), (ins RO:$rs, uimm16:$imm16), + !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>; // Mul, Div class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, list<Register> DefRegs> : @@ -914,6 +917,18 @@ def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>; def SYNC : SYNC_FT, SYNC_FM; def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; +def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; +def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; +def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>; +def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>; +def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>; + +def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>; +def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>; +def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>; +def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>; +def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>; +def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>; def BREAK : BRK_FT<"break">, BRK_FM<0xd>; def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; @@ -1093,6 +1108,13 @@ def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; def : InstAlias<"break", (BREAK 0, 0), 1>; def : InstAlias<"ei", (EI ZERO), 1>; def : InstAlias<"di", (DI ZERO), 1>; + +def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// |