[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)

Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 77 insertions, 0 deletions

diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td
index 7cc1a88bd6..6f1e58f2c6 100644
--- a/lib/Target/Mips/MipsMSAInstrFormats.td
+++ b/lib/Target/Mips/MipsMSAInstrFormats.td
@@ -21,14 +21,91 @@ class PseudoMSA<dag outs, dag ins, list<dag> pattern,
   let Predicates = [HasMSA];
 }
 
+class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
+  let Inst{25-23} = major;
+  let Inst{22-19} = 0b1110;
+  let Inst{5-0} = minor;
+}
+
+class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
+  let Inst{25-23} = major;
+  let Inst{22-20} = 0b110;
+  let Inst{5-0} = minor;
+}
+
+class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
+  let Inst{25-23} = major;
+  let Inst{22-21} = 0b10;
+  let Inst{5-0} = minor;
+}
+
+class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
+  let Inst{25-23} = major;
+  let Inst{22} = 0b0;
+  let Inst{5-0} = minor;
+}
+
+class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
+  let Inst{25-18} = major;
+  let Inst{17-16} = df;
+  let Inst{5-0} = minor;
+}
+
+class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
+  let Inst{25-17} = major;
+  let Inst{16} = df;
+  let Inst{5-0} = minor;
+}
+
 class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
   let Inst{25-23} = major;
   let Inst{22-21} = df;
   let Inst{5-0} = minor;
 }
 
+class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
+  let Inst{25-22} = major;
+  let Inst{21} = df;
+  let Inst{5-0} = minor;
+}
+
+class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
+  let Inst{25-22} = major;
+  let Inst{21-20} = 0b00;
+  let Inst{5-0} = minor;
+}
+
+class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
+  let Inst{25-22} = major;
+  let Inst{21-19} = 0b100;
+  let Inst{5-0} = minor;
+}
+
+class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
+  let Inst{25-22} = major;
+  let Inst{21-18} = 0b1100;
+  let Inst{5-0} = minor;
+}
+
+class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
+  let Inst{25-22} = major;
+  let Inst{21-17} = 0b11100;
+  let Inst{5-0} = minor;
+}
+
 class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
   let Inst{25-23} = major;
   let Inst{22-21} = df;
   let Inst{5-0} = minor;
 }
+
+class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
+  let Inst{25-24} = major;
+  let Inst{5-0} = minor;
+}
+
+class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
+  let Inst{25-23} = major;
+  let Inst{22-21} = df;
+  let Inst{5-0} = minor;
+}