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| author | Matheus Almeida <matheus.almeida@imgtec.com> | 2013-12-05 11:06:22 +0000 |
|---|---|---|
| committer | Matheus Almeida <matheus.almeida@imgtec.com> | 2013-12-05 11:06:22 +0000 |
| commit | 4faa2b38fb0fa98fd3f157a5456c828c4e762dce (patch) | |
| tree | 34e88312dc314abf0ad04af96a779388192bd6f1 /lib/Target/Mips/MipsMSAInstrInfo.td | |
| parent | 52123d184232683deee6b51ab2245b186829f408 (diff) | |
| download | llvm-4faa2b38fb0fa98fd3f157a5456c828c4e762dce.tar.gz llvm-4faa2b38fb0fa98fd3f157a5456c828c4e762dce.tar.bz2 llvm-4faa2b38fb0fa98fd3f157a5456c828c4e762dce.tar.xz | |
[mips][msa] Fix issue with immediate fields of LD/ST instructions
not being correctly encoded/decoded.
In more detail, immediate fields of LD/ST instructions should be
divided/multiplied by the size of the data format before encoding and
after decoding, respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196494 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsMSAInstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 9089be2abc..7a588f6e95 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -2269,7 +2269,7 @@ class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d, class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, - Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm, + Operand MemOpnd = mem_msa, ComplexPattern Addr = addrRegImm, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addr); @@ -2590,7 +2590,7 @@ class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d, class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, - Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm, + Operand MemOpnd = mem_msa, ComplexPattern Addr = addrRegImm, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); |