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author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-10-30 14:45:14 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-10-30 14:45:14 +0000 |
commit | 6ff1ef9931b50763a40e9ae8696cfab9e25cf4de (patch) | |
tree | 3a212fbec02bbe355534190b163a19779eb8a134 /lib/Target/Mips/MipsMSAInstrInfo.td | |
parent | a7c3cac87118c3e409a7fc889090c5ffe242985e (diff) | |
download | llvm-6ff1ef9931b50763a40e9ae8696cfab9e25cf4de.tar.gz llvm-6ff1ef9931b50763a40e9ae8696cfab9e25cf4de.tar.bz2 llvm-6ff1ef9931b50763a40e9ae8696cfab9e25cf4de.tar.xz |
[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.
It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().
Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsMSAInstrInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 61 |
1 files changed, 45 insertions, 16 deletions
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 65d85e34ee..a393fdc45e 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -315,6 +315,18 @@ def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", [build_vector, bitconvert]>; +// Any build_vector that is a constant splat with only a consecutive sequence +// of left-most bits set. +def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1, + "selectVSplatMaskL", + [build_vector, bitconvert]>; + +// Any build_vector that is a constant splat with only a consecutive sequence +// of right-most bits set. +def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1, + "selectVSplatMaskR", + [build_vector, bitconvert]>; + def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt), (fsub node:$wd, (fmul node:$ws, node:$wt))>; @@ -1079,6 +1091,31 @@ class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, InstrItinClass Itinerary = itin; } +class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, + ComplexPattern Mask, RegisterOperand ROWD, + RegisterOperand ROWS = ROWD, + InstrItinClass itin = NoItinerary> { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$wd_in), + ROWS:$ws))]; + InstrItinClass Itinerary = itin; + string Constraints = "$wd = $wd_in"; +} + +class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, + RegisterOperand ROWD, + RegisterOperand ROWS = ROWD, + InstrItinClass itin = NoItinerary> : + MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>; + +class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, + RegisterOperand ROWD, + RegisterOperand ROWS = ROWD, + InstrItinClass itin = NoItinerary> : + MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>; + class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, SplatComplexPattern SplatImm, RegisterOperand ROWD, RegisterOperand ROWS = ROWD, @@ -1486,28 +1523,20 @@ class BINSL_H_DESC : MSA_3R_DESC_BASE<"binsl.h", int_mips_binsl_h, MSA128HOpnd>; class BINSL_W_DESC : MSA_3R_DESC_BASE<"binsl.w", int_mips_binsl_w, MSA128WOpnd>; class BINSL_D_DESC : MSA_3R_DESC_BASE<"binsl.d", int_mips_binsl_d, MSA128DOpnd>; -class BINSLI_B_DESC : MSA_BIT_B_DESC_BASE<"binsli.b", int_mips_binsli_b, - MSA128BOpnd>; -class BINSLI_H_DESC : MSA_BIT_H_DESC_BASE<"binsli.h", int_mips_binsli_h, - MSA128HOpnd>; -class BINSLI_W_DESC : MSA_BIT_W_DESC_BASE<"binsli.w", int_mips_binsli_w, - MSA128WOpnd>; -class BINSLI_D_DESC : MSA_BIT_D_DESC_BASE<"binsli.d", int_mips_binsli_d, - MSA128DOpnd>; +class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>; +class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>; +class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>; +class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>; class BINSR_B_DESC : MSA_3R_DESC_BASE<"binsr.b", int_mips_binsr_b, MSA128BOpnd>; class BINSR_H_DESC : MSA_3R_DESC_BASE<"binsr.h", int_mips_binsr_h, MSA128HOpnd>; class BINSR_W_DESC : MSA_3R_DESC_BASE<"binsr.w", int_mips_binsr_w, MSA128WOpnd>; class BINSR_D_DESC : MSA_3R_DESC_BASE<"binsr.d", int_mips_binsr_d, MSA128DOpnd>; -class BINSRI_B_DESC : MSA_BIT_B_DESC_BASE<"binsri.b", int_mips_binsri_b, - MSA128BOpnd>; -class BINSRI_H_DESC : MSA_BIT_H_DESC_BASE<"binsri.h", int_mips_binsri_h, - MSA128HOpnd>; -class BINSRI_W_DESC : MSA_BIT_W_DESC_BASE<"binsri.w", int_mips_binsri_w, - MSA128WOpnd>; -class BINSRI_D_DESC : MSA_BIT_D_DESC_BASE<"binsri.d", int_mips_binsri_d, - MSA128DOpnd>; +class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>; +class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>; +class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>; +class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>; class BMNZ_V_DESC : MSA_VEC_DESC_BASE<"bmnz.v", int_mips_bmnz_v, MSA128BOpnd>; |