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| author | Evan Cheng <evan.cheng@apple.com> | 2007-07-19 01:14:50 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-07-19 01:14:50 +0000 |
| commit | 64d80e3387f328d21cd9cc06464b5de7861e3f27 (patch) | |
| tree | 203a9dfb41eba2fd8bd65a1e8bb80f73e36c0771 /lib/Target/Mips/MipsRegisterInfo.h | |
| parent | 4558b807a2076e199bcb019f5edc9eabbc5922c1 (diff) | |
| download | llvm-64d80e3387f328d21cd9cc06464b5de7861e3f27.tar.gz llvm-64d80e3387f328d21cd9cc06464b5de7861e3f27.tar.bz2 llvm-64d80e3387f328d21cd9cc06464b5de7861e3f27.tar.xz | |
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.h')
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index d84194f31a..ebc0318b88 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -49,9 +49,10 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo { const TargetRegisterClass *RC) const; - const unsigned *getCalleeSavedRegs() const; + const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; - const TargetRegisterClass* const* getCalleeSavedRegClasses() const; + const TargetRegisterClass* const* + getCalleeSavedRegClasses(const MachineFunction* MF = 0) const; BitVector getReservedRegs(const MachineFunction &MF) const; |