diff options
author | Akira Hatanaka <ahatanak@gmail.com> | 2011-04-15 21:51:11 +0000 |
---|---|---|
committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-04-15 21:51:11 +0000 |
commit | 4552c9a3b34ad9b2085635266348d0d9b95514a6 (patch) | |
tree | d7e5b6178d0738dff93e314e346515728077158f /lib/Target/Mips/MipsRegisterInfo.td | |
parent | 0cb11ac32fc09c5db42fb801db242ac9fb51f6b1 (diff) | |
download | llvm-4552c9a3b34ad9b2085635266348d0d9b95514a6.tar.gz llvm-4552c9a3b34ad9b2085635266348d0d9b95514a6.tar.bz2 llvm-4552c9a3b34ad9b2085635266348d0d9b95514a6.tar.xz |
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index d015bf568c..9f9cae7d11 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -1,15 +1,15 @@ -//===- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// +//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// // Declarations that describe the MIPS register file -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// // We have banks of 32 registers each. class MipsReg<string n> : Register<n> { @@ -44,9 +44,9 @@ class AFPR<bits<5> num, string n, list<Register> subregs> let SubRegIndices = [sub_fpeven, sub_fpodd]; } -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// // Registers -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// let Namespace = "Mips" in { @@ -145,9 +145,9 @@ let Namespace = "Mips" in { def FCR31 : Register<"31">; } -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// // Register Classes -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// def CPURegs : RegisterClass<"Mips", [i32], 32, // Return Values and Arguments |