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authorAkira Hatanaka <ahatanak@gmail.com>2011-09-22 17:57:32 +0000
committerAkira Hatanaka <ahatanak@gmail.com>2011-09-22 17:57:32 +0000
commit95a091a0b65d1b4a27eedd9a0c96da319209b686 (patch)
treef69a0a4cfc5a437fe68a8bcc099017811cd523a6 /lib/Target/Mips/MipsRegisterInfo.td
parent711395527e6b19d4bf26e22586f2c13591970ba6 (diff)
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Define a new sub-register index sub_32 for accessing the 32-bit sub-register of
a 64-bit integer register. Move the subreg index definitions to the beginning of the file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140319 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
-rw-r--r--lib/Target/Mips/MipsRegisterInfo.td9
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index de0ccbb4fd..62210210dd 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -10,6 +10,11 @@
//===----------------------------------------------------------------------===//
// Declarations that describe the MIPS register file
//===----------------------------------------------------------------------===//
+let Namespace = "Mips" in {
+def sub_fpeven : SubRegIndex;
+def sub_fpodd : SubRegIndex;
+def sub_32 : SubRegIndex;
+}
// We have banks of 32 registers each.
class MipsReg<string n> : Register<n> {
@@ -34,10 +39,6 @@ class FPR<bits<5> num, string n> : MipsReg<n> {
}
// Mips 64-bit (aliased) FPU Registers
-let Namespace = "Mips" in {
-def sub_fpeven : SubRegIndex;
-def sub_fpodd : SubRegIndex;
-}
class AFPR<bits<5> num, string n, list<Register> subregs>
: MipsRegWithSubRegs<n, subregs> {
let Num = num;