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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 01:21:14 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 01:21:14 +0000 |
| commit | b555609e73f5091bf8180c0875fb1fa6c5ad0e7a (patch) | |
| tree | 96d997b82dbd5e9fa80e40dd406b0e55db187b2d /lib/Target/Mips/MipsRegisterInfo.td | |
| parent | a4e4ffd389497eb28f5fe91521fb71da4340e5d6 (diff) | |
| download | llvm-b555609e73f5091bf8180c0875fb1fa6c5ad0e7a.tar.gz llvm-b555609e73f5091bf8180c0875fb1fa6c5ad0e7a.tar.bz2 llvm-b555609e73f5091bf8180c0875fb1fa6c5ad0e7a.tar.xz | |
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index be78a22662..576110d77c 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -34,14 +34,9 @@ class FPR<bits<5> num, string n> : MipsReg<n> { } // Mips 64-bit (aliased) FPU Registers -let Namespace = "Mips" in { -def sub_fpeven : SubRegIndex; -def sub_fpodd : SubRegIndex; -} -class AFPR<bits<5> num, string n, list<Register> subregs> +class AFPR<bits<5> num, string n, list<Register> subregs> : MipsRegWithSubRegs<n, subregs> { let Num = num; - let SubRegIndices = [sub_fpeven, sub_fpodd]; } //===----------------------------------------------------------------------===// @@ -146,6 +141,25 @@ let Namespace = "Mips" in { } //===----------------------------------------------------------------------===// +// Subregister Set Definitions +//===----------------------------------------------------------------------===// + +let Namespace = "Mips" in { +def sub_fpeven : SubRegIndex; +def sub_fpodd : SubRegIndex; +} + +def : SubRegSet<sub_fpeven, [D0, D1, D2, D3, D4, D5, D6, D7, + D8, D9, D10, D11, D12, D13, D14, D15], + [F0, F2, F4, F6, F8, F10, F12, F14, + F16, F18, F20, F22, F24, F26, F28, F30]>; + +def : SubRegSet<sub_fpodd, [D0, D1, D2, D3, D4, D5, D6, D7, + D8, D9, D10, D11, D12, D13, D14, D15], + [F1, F3, F5, F7, F9, F11, F13, F15, + F17, F19, F21, F23, F25, F27, F29, F31]>; + +//===----------------------------------------------------------------------===// // Register Classes //===----------------------------------------------------------------------===// |