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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 23:28:14 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 23:28:14 +0000 |
commit | f28987b76e758b5f2fcc2c5d2c8e073df54ca91e (patch) | |
tree | 8f60dc5b88bbfc1192d2a780d9a5ee6702535e5f /lib/Target/Mips/MipsRegisterInfo.td | |
parent | f14bacc862eb69c7c779858746cc020386ce5590 (diff) | |
download | llvm-f28987b76e758b5f2fcc2c5d2c8e073df54ca91e.tar.gz llvm-f28987b76e758b5f2fcc2c5d2c8e073df54ca91e.tar.bz2 llvm-f28987b76e758b5f2fcc2c5d2c8e073df54ca91e.tar.xz |
Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 28 |
1 files changed, 10 insertions, 18 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index e97d4505eb..f0db518b75 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -157,15 +157,15 @@ let Namespace = "Mips" in { // Register Classes //===----------------------------------------------------------------------===// -def CPURegs : RegisterClass<"Mips", [i32], 32, +def CPURegs : RegisterClass<"Mips", [i32], 32, (add // Return Values and Arguments - [V0, V1, A0, A1, A2, A3, + V0, V1, A0, A1, A2, A3, // Not preserved across procedure calls T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, // Callee save S0, S1, S2, S3, S4, S5, S6, S7, // Reserved - ZERO, AT, K0, K1, GP, SP, FP, RA]>; + ZERO, AT, K0, K1, GP, SP, FP, RA)>; // 64bit fp: // * FGR64 - 32 64-bit registers @@ -174,33 +174,25 @@ def CPURegs : RegisterClass<"Mips", [i32], 32, // 32bit fp: // * FGR32 - 16 32-bit even registers // * FGR32 - 32 32-bit registers (single float only mode) -def FGR32 : RegisterClass<"Mips", [f32], 32, - // Return Values and Arguments - [F0, F1, F2, F3, F12, F13, F14, F15, - // Not preserved across procedure calls - F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19, - // Callee save - F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, - // Reserved - F31]>; +def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; -def AFGR64 : RegisterClass<"Mips", [f64], 64, +def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Return Values and Arguments - [D0, D1, D6, D7, + D0, D1, D6, D7, // Not preserved across procedure calls D2, D3, D4, D5, D8, D9, // Callee save D10, D11, D12, D13, D14, // Reserved - D15]> { + D15)> { let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)]; } // Condition Register for floating point operations -def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]>; +def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>; // Hi/Lo Registers -def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>; +def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; // Hardware registers -def HWRegs : RegisterClass<"Mips", [i32], 32, [HWR29]>; +def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; |