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| author | Akira Hatanaka <ahatanak@gmail.com> | 2011-04-15 21:00:26 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-04-15 21:00:26 +0000 |
| commit | 0bf3dfbef60e36827df9c7e12b62503f1e345cd0 (patch) | |
| tree | 2d216dbfb7ecf59bc8c895297ca198d605f6f844 /lib/Target/Mips/MipsSchedule.td | |
| parent | b485de5d8c3fe0c62c0b07f63f64bd10f6803c17 (diff) | |
| download | llvm-0bf3dfbef60e36827df9c7e12b62503f1e345cd0.tar.gz llvm-0bf3dfbef60e36827df9c7e12b62503f1e345cd0.tar.bz2 llvm-0bf3dfbef60e36827df9c7e12b62503f1e345cd0.tar.xz | |
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSchedule.td')
| -rw-r--r-- | lib/Target/Mips/MipsSchedule.td | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td index 00be8ee944..bb7d5f1a88 100644 --- a/lib/Target/Mips/MipsSchedule.td +++ b/lib/Target/Mips/MipsSchedule.td @@ -1,21 +1,21 @@ -//===- MipsSchedule.td - Mips Scheduling Definitions -------*- tablegen -*-===// +//===- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Functional units across Mips chips sets. Based on GCC/Mips backend files. -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// def ALU : FuncUnit; def IMULDIV : FuncUnit; -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Instruction Itinerary classes used for Mips -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// def IIAlu : InstrItinClass; def IILoad : InstrItinClass; def IIStore : InstrItinClass; @@ -37,9 +37,9 @@ def IIFsqrtDouble : InstrItinClass; def IIFrecipFsqrtStep : InstrItinClass; def IIPseudo : InstrItinClass; -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Mips Generic instruction itineraries. -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>, InstrItinData<IILoad , [InstrStage<3, [ALU]>]>, |