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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-01-21 12:38:07 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-01-21 12:38:07 +0000 |
| commit | b029a0ec6a89efa96aabf759f7526ea2a2f30d6b (patch) | |
| tree | 2b68a7d9b5f258e8f4bba4410e21509f2e059853 /lib/Target/Mips/MipsSchedule.td | |
| parent | 65d38c3fcd1468f9129284a770103d4ec30363b3 (diff) | |
| download | llvm-b029a0ec6a89efa96aabf759f7526ea2a2f30d6b.tar.gz llvm-b029a0ec6a89efa96aabf759f7526ea2a2f30d6b.tar.bz2 llvm-b029a0ec6a89efa96aabf759f7526ea2a2f30d6b.tar.xz | |
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS]
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199732 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSchedule.td')
| -rw-r--r-- | lib/Target/Mips/MipsSchedule.td | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td index d31db0706c..472722c1bc 100644 --- a/lib/Target/Mips/MipsSchedule.td +++ b/lib/Target/Mips/MipsSchedule.td @@ -20,7 +20,6 @@ def IIAlu : InstrItinClass; def IILoad : InstrItinClass; def IIStore : InstrItinClass; def IIBranch : InstrItinClass; -def IIFadd : InstrItinClass; def IIFmulSingle : InstrItinClass; def IIFmulDouble : InstrItinClass; def IIFdivSingle : InstrItinClass; @@ -37,6 +36,8 @@ def II_ABS : InstrItinClass; def II_ADDI : InstrItinClass; def II_ADDIU : InstrItinClass; def II_ADDU : InstrItinClass; +def II_ADD_D : InstrItinClass; +def II_ADD_S : InstrItinClass; def II_AND : InstrItinClass; def II_ANDI : InstrItinClass; def II_CEIL : InstrItinClass; @@ -112,6 +113,8 @@ def II_SRAV : InstrItinClass; def II_SRL : InstrItinClass; def II_SRLV : InstrItinClass; def II_SUBU : InstrItinClass; +def II_SUB_D : InstrItinClass; +def II_SUB_S : InstrItinClass; def II_TRUNC : InstrItinClass; def II_XOR : InstrItinClass; def II_XORI : InstrItinClass; @@ -200,7 +203,10 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_MOVZ_S , [InstrStage<2, [ALU]>]>, InstrItinData<II_C_CC_S , [InstrStage<3, [ALU]>]>, InstrItinData<II_C_CC_D , [InstrStage<3, [ALU]>]>, - InstrItinData<IIFadd , [InstrStage<4, [ALU]>]>, + InstrItinData<II_ADD_D , [InstrStage<4, [ALU]>]>, + InstrItinData<II_ADD_S , [InstrStage<4, [ALU]>]>, + InstrItinData<II_SUB_D , [InstrStage<4, [ALU]>]>, + InstrItinData<II_SUB_S , [InstrStage<4, [ALU]>]>, InstrItinData<IIFmulSingle , [InstrStage<7, [ALU]>]>, InstrItinData<IIFmulDouble , [InstrStage<8, [ALU]>]>, InstrItinData<IIFdivSingle , [InstrStage<23, [ALU]>]>, |