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authorAkira Hatanaka <ahatanaka@mips.com>2012-03-28 00:24:17 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-03-28 00:24:17 +0000
commit81a424b3c5e7be03d66d5c7fd241f2aac47d1a2c (patch)
treeaa1a5b4820aa79572d0b95dfc49b5dce47ea192d /lib/Target/Mips/MipsSubtarget.h
parent37ac18ef2f13a8060b745e6d3c4622bafdd4f47b (diff)
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Turn on post register allocation scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153554 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSubtarget.h')
-rw-r--r--lib/Target/Mips/MipsSubtarget.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index ba0bbacb5a..7faf77baa6 100644
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -89,6 +89,9 @@ protected:
InstrItineraryData InstrItins;
public:
+ virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+ AntiDepBreakMode& Mode,
+ RegClassVector& CriticalPathRCs) const;
/// Only O32 and EABI supported right now.
bool isABI_EABI() const { return MipsABI == EABI; }