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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-01-16 16:19:38 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-01-16 16:19:38 +0000 |
| commit | 1a6226f236c102bba93162f0f1947f888ecbfec8 (patch) | |
| tree | df48d58b2b763af60db391482b7ec406e4283557 /lib/Target/Mips | |
| parent | ba8f9dde320d004b915d44d2f39203bbbdcb145c (diff) | |
| download | llvm-1a6226f236c102bba93162f0f1947f888ecbfec8.tar.gz llvm-1a6226f236c102bba93162f0f1947f888ecbfec8.tar.bz2 llvm-1a6226f236c102bba93162f0f1947f888ecbfec8.tar.xz | |
[mips][sched] Split IIseb into II_SEB and II_SEH
No functional change since there are no InstrItinData's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199396 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
| -rw-r--r-- | lib/Target/Mips/MicroMipsInstrInfo.td | 4 | ||||
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 4 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 9 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSchedule.td | 3 |
4 files changed, 11 insertions, 9 deletions
diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index ac634c9b15..47c6f26544 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -188,8 +188,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>; /// Sign Ext In Register Instructions. - def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM_MM<0x0ac>; - def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM_MM<0x0ec>; + def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM_MM<0x0ac>; + def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM_MM<0x0ec>; /// Word Swap Bytes Within Halfwords def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>; diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index f2055df86c..b6ecb12259 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -192,8 +192,8 @@ def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>; def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>; /// Sign Ext In Register Instructions. -def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>; -def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd>, SEB_FM<0x18, 0x20>; +def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>; +def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>; } /// Count Leading diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 3dc1624ddf..4e56132e61 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -768,9 +768,10 @@ class CountLeading1<string opstr, RegisterOperand RO>: // Sign Extend in Register. -class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> : +class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO, + InstrItinClass itin> : InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), - [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> { + [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> { let Predicates = [HasSEInReg, HasStdEnc]; } @@ -1082,8 +1083,8 @@ def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>; def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>; /// Sign Ext In Register Instructions. -def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>; -def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>; +def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>; +def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>; /// Count Leading def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>; diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td index b7f50cab1a..a62dfbd198 100644 --- a/lib/Target/Mips/MipsSchedule.td +++ b/lib/Target/Mips/MipsSchedule.td @@ -25,7 +25,6 @@ def IIHiLo : InstrItinClass; def IIImul : InstrItinClass; def IIImult : InstrItinClass; def IIIdiv : InstrItinClass; -def IIseb : InstrItinClass; def IIslt : InstrItinClass; def IIFcvt : InstrItinClass; def IIFmove : InstrItinClass; @@ -76,6 +75,8 @@ def II_ORI : InstrItinClass; def II_RDHWR : InstrItinClass; def II_ROTR : InstrItinClass; def II_ROTRV : InstrItinClass; +def II_SEB : InstrItinClass; +def II_SEH : InstrItinClass; def II_SLL : InstrItinClass; def II_SLLV : InstrItinClass; def II_SRA : InstrItinClass; |