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author | Reed Kotler <rkotler@mips.com> | 2014-06-08 03:30:32 +0000 |
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committer | Reed Kotler <rkotler@mips.com> | 2014-06-08 03:30:32 +0000 |
commit | 4a0c1d135eb8d3f1a3e71bb5aed02f59bc062125 (patch) | |
tree | 13920c79f2b069533527d442ca7e40ed0da1939d /lib/Target/Mips | |
parent | cf7742cb63ea34798c72670bf8c8c1fd93d2577c (diff) | |
download | llvm-4a0c1d135eb8d3f1a3e71bb5aed02f59bc062125.tar.gz llvm-4a0c1d135eb8d3f1a3e71bb5aed02f59bc062125.tar.bz2 llvm-4a0c1d135eb8d3f1a3e71bb5aed02f59bc062125.tar.xz |
Do materialize for floating point
Summary:
start to do simple constants
finish simplestore
add test case
format
Merge branch 'master' into 1756_8
Add basic functionality for assignment of ints. This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel
Merge branch 'master' into 1756_8
Add basic functionality for assignment of ints. This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel
in progress
finish integer materialize
test cases
test cases
in progress
Finish up fast-isel materialize for ints.
Finish materialize for ints
test cases
simplestorei.ll
Merge branch 'master' into 1756_8
fix fp constants for fast-isel
Merge branch '1758_1' of dmz-portal.mips.com:llvm into 1758_1
in progress
lastest for fp materialization
clean up
Merge branch 'master' into 1758_1
formatting
add test case
finish test case
Merge branch 'master' into 1758_2
Test Plan:
simplestore.ll
simplestore.ll
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D3659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210414 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
-rw-r--r-- | lib/Target/Mips/MipsFastISel.cpp | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp index 448698e2de..9a60aa7b9f 100644 --- a/lib/Target/Mips/MipsFastISel.cpp +++ b/lib/Target/Mips/MipsFastISel.cpp @@ -167,9 +167,14 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr, // // more cases will be handled here in following patches. // - if (VT != MVT::i32) + if (VT == MVT::i32) + EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset); + else if (VT == MVT::f32) + EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset); + else if (VT == MVT::f64) + EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset); + else return false; - EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset); return true; } @@ -229,6 +234,22 @@ bool MipsFastISel::TargetSelectInstruction(const Instruction *I) { } unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) { + int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); + if (VT == MVT::f32) { + const TargetRegisterClass *RC = &Mips::FGR32RegClass; + unsigned DestReg = createResultReg(RC); + unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass); + EmitInst(Mips::MTC1, DestReg).addReg(TempReg); + return DestReg; + } else if (VT == MVT::f64) { + const TargetRegisterClass *RC = &Mips::AFGR64RegClass; + unsigned DestReg = createResultReg(RC); + unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); + unsigned TempReg2 = + Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); + EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); + return DestReg; + } return 0; } |