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author | Reed Kotler <rkotler@mips.com> | 2013-02-20 05:45:15 +0000 |
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committer | Reed Kotler <rkotler@mips.com> | 2013-02-20 05:45:15 +0000 |
commit | 65692c809efa46337bf80f12b1795e785a6e7207 (patch) | |
tree | f9f6d1833ac565de99fd963ba50bb3ba60bd36ef /lib/Target/Mips | |
parent | d326d05fb9c794e93fc7fc0601028f196600f7e2 (diff) | |
download | llvm-65692c809efa46337bf80f12b1795e785a6e7207.tar.gz llvm-65692c809efa46337bf80f12b1795e785a6e7207.tar.bz2 llvm-65692c809efa46337bf80f12b1795e785a6e7207.tar.xz |
Expand pseudos/macros:
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175593 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.cpp | 56 | ||||
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.h | 14 | ||||
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 50 |
3 files changed, 110 insertions, 10 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp index 22cb9638bc..eacc8fc04a 100644 --- a/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/lib/Target/Mips/Mips16InstrInfo.cpp @@ -184,6 +184,18 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { case Mips::RetRA16: ExpandRetRA16(MBB, MI, Mips::JrcRa16); break; + case Mips::SltCCRxRy16: + ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltRxRy16); + break; + case Mips::SltiCCRxImmX16: + ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiRxImm16, Mips::SltiRxImmX16); + break; + case Mips::SltiuCCRxImmX16: + ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiuRxImm16, Mips::SltiuRxImmX16); + break; + case Mips::SltuCCRxRy16: + ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltuRxRy16); + break; } MBB.erase(MI); @@ -474,6 +486,30 @@ void Mips16InstrInfo::ExpandFEXT_T8I8I16_ins( BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target); } +void Mips16InstrInfo::ExpandFEXT_CCRX16_ins( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned SltOpc) const { + unsigned CC = I->getOperand(0).getReg(); + unsigned regX = I->getOperand(1).getReg(); + unsigned regY = I->getOperand(2).getReg(); + BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addReg(regY); + BuildMI(MBB, I, I->getDebugLoc(), + get(Mips::MoveR3216), CC).addReg(Mips::T8); + +} +void Mips16InstrInfo::ExpandFEXT_CCRXI16_ins( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned SltiOpc, unsigned SltiXOpc) const { + unsigned CC = I->getOperand(0).getReg(); + unsigned regX = I->getOperand(1).getReg(); + int64_t Imm = I->getOperand(2).getImm(); + unsigned SltOpc = whichOp8u_or_16simm(SltiOpc, SltiXOpc, Imm); + BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addImm(Imm); + BuildMI(MBB, I, I->getDebugLoc(), + get(Mips::MoveR3216), CC).addReg(Mips::T8); + +} + const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const { if (validSpImm8(Imm)) return get(Mips::AddiuSpImm16); @@ -487,6 +523,26 @@ void Mips16InstrInfo::BuildAddiuSpImm BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm); } +unsigned Mips16InstrInfo::whichOp8_or_16uimm + (unsigned shortOp, unsigned longOp, int64_t Imm) { + if (isUInt<8>(Imm)) + return shortOp; + else if (isUInt<16>(Imm)) + return longOp; + else + llvm_unreachable("immediate field not usable"); +} + +unsigned Mips16InstrInfo::whichOp8u_or_16simm + (unsigned shortOp, unsigned longOp, int64_t Imm) { + if (isUInt<8>(Imm)) + return shortOp; + else if (isInt<16>(Imm)) + return longOp; + else + llvm_unreachable("immediate field not usable"); +} + const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) { return new Mips16InstrInfo(TM); } diff --git a/lib/Target/Mips/Mips16InstrInfo.h b/lib/Target/Mips/Mips16InstrInfo.h index 2699a1c39e..0048fff5e6 100644 --- a/lib/Target/Mips/Mips16InstrInfo.h +++ b/lib/Target/Mips/Mips16InstrInfo.h @@ -123,6 +123,20 @@ private: MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const; + void ExpandFEXT_CCRX16_ins( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned SltOpc) const; + + void ExpandFEXT_CCRXI16_ins( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned SltiOpc, unsigned SltiXOpc) const; + + static unsigned + whichOp8_or_16uimm (unsigned shortOp, unsigned longOp, int64_t Imm); + + static unsigned + whichOp8u_or_16simm (unsigned shortOp, unsigned longOp, int64_t Imm); + }; } diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 0d90df41fe..1cb4a0edfd 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -59,7 +59,16 @@ class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2, class FRI16_ins<bits<5> op, string asmstr, InstrItinClass itin>: FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; - + +class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2, + InstrItinClass itin>: + FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm), + !strconcat(asmstr, asmstr2), [], itin>; + +class FRI16R_ins<bits<5> op, string asmstr, + InstrItinClass itin>: + FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; + class F2RI16_ins<bits<5> _op, string asmstr, InstrItinClass itin>: FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), @@ -140,6 +149,15 @@ class FEXT_RI16_ins<bits<5> _op, string asmstr, InstrItinClass itin>: FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; +class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2, + InstrItinClass itin>: + FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm), + !strconcat(asmstr, asmstr2), [], itin>; + +class FEXT_RI16R_ins<bits<5> _op, string asmstr, + InstrItinClass itin>: + FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>; + class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; @@ -384,7 +402,7 @@ class SeliT<string op1, string op2>: // // class SelT<string op1, string op2>: - MipsPseudo16<(outs CPU16Regs:$rd_), + MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, CPU16Regs:$rl, CPU16Regs:$rr), !strconcat(op2, @@ -692,6 +710,13 @@ def LhuRxRyOffMemX16: // // Format: LI rx, immediate MIPS16e +// Purpose: Load Immediate +// To load a constant into a GPR. +// +def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>; + +// +// Format: LI rx, immediate MIPS16e // Purpose: Load Immediate (Extended) // To load a constant into a GPR. // @@ -1017,7 +1042,7 @@ def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; // To record the result of a less-than comparison with a constant. // // -def SltiRxImm16: FRI16_ins<0b01010, "slti", IIAlu> { +def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> { let Defs = [T8]; } @@ -1027,7 +1052,7 @@ def SltiRxImm16: FRI16_ins<0b01010, "slti", IIAlu> { // To record the result of a less-than comparison with a constant. // // -def SltiRxImmX16: FEXT_RI16_ins<0b01010, "slti", IIAlu> { +def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> { let Defs = [T8]; } @@ -1038,7 +1063,7 @@ def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">; // To record the result of a less-than comparison with a constant. // // -def SltiuRxImm16: FRI16_ins<0b01011, "sltiu", IIAlu> { +def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> { let Defs = [T8]; } @@ -1048,7 +1073,7 @@ def SltiuRxImm16: FRI16_ins<0b01011, "sltiu", IIAlu> { // To record the result of a less-than comparison with a constant. // // -def SltiuRxImmX16: FEXT_RI16_ins<0b01011, "sltiu", IIAlu> { +def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> { let Defs = [T8]; } // @@ -1063,7 +1088,9 @@ def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">; // Purpose: Set on Less Than // To record the result of a less-than comparison. // -def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>; +def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>{ + let Defs = [T8]; +} def SltCCRxRy16: FCCRR16_ins<"slt">; @@ -1071,10 +1098,13 @@ def SltCCRxRy16: FCCRR16_ins<"slt">; // Purpose: Set on Less Than Unsigned // To record the result of an unsigned less-than comparison. // -def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>; +def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>{ + let Defs = [T8]; +} def SltuRxRyRz16: FRRTR16_ins<"sltu"> { let isCodeGenOnly=1; + let Defs = [T8]; } @@ -1648,7 +1678,7 @@ def: Mips16Pat // def: Mips16Pat <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), - (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; + (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>; // // setlt @@ -1708,7 +1738,7 @@ def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), // hi/lo relocs -def : Mips16Pat<(MipsHi tglobaladdr:$in), +def : Mips16Pat<(MipsHi tglobaladdr:$in), (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>; def : Mips16Pat<(MipsHi tjumptable:$in), (SllX16 (LiRxImmX16 tjumptable:$in), 16)>; |