Revert "Do materialize for floating point"

1) The commit was made despite profound lack of understanding:

   "I did not understand the comment about using dyn_cast instead of isa. I will
   commit as is and make the update after. You can explain what you meant to me."

   Commit first, understand later isn't OK.

2) Review comments were simply ignored:

   "Can you edit the summary to describe what the patch is for? It appears to be
   a list of commits at the moment."

3) The patch got LGTM'd off-list without any indication of readiness.

4) The public mailing list was excluded from patch review so all of this was
   hidden from the community.

This reverts commit r210414.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210424 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 2 insertions, 23 deletions

diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp
index 9a60aa7b9f..448698e2de 100644
--- a/lib/Target/Mips/MipsFastISel.cpp
+++ b/lib/Target/Mips/MipsFastISel.cpp
@@ -167,14 +167,9 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
   //
   // more cases will be handled here in following patches.
   //
-  if (VT == MVT::i32)
-    EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
-  else if (VT == MVT::f32)
-    EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset);
-  else if (VT == MVT::f64)
-    EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset);
-  else
+  if (VT != MVT::i32)
     return false;
+  EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
   return true;
 }
 
@@ -234,22 +229,6 @@ bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
 }
 
 unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
-  int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
-  if (VT == MVT::f32) {
-    const TargetRegisterClass *RC = &Mips::FGR32RegClass;
-    unsigned DestReg = createResultReg(RC);
-    unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
-    EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
-    return DestReg;
-  } else if (VT == MVT::f64) {
-    const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
-    unsigned DestReg = createResultReg(RC);
-    unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
-    unsigned TempReg2 =
-        Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
-    EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
-    return DestReg;
-  }
   return 0;
 }