summaryrefslogtreecommitdiff
path: root/lib/Target/Mips
diff options
context:
space:
mode:
authorDaniel Sanders <daniel.sanders@imgtec.com>2014-02-20 13:13:33 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2014-02-20 13:13:33 +0000
commit7934a2a9f1d8d8dc220f5b25a303a770306d51d1 (patch)
treee8bb4ab5dcec9b659b8a118305a2151a875d680f /lib/Target/Mips
parentb584e193b59701a4aaf3173cbe5ae022b3f53843 (diff)
downloadllvm-7934a2a9f1d8d8dc220f5b25a303a770306d51d1.tar.gz
llvm-7934a2a9f1d8d8dc220f5b25a303a770306d51d1.tar.bz2
llvm-7934a2a9f1d8d8dc220f5b25a303a770306d51d1.tar.xz
[mips] Make mips64 the default CPU for the mips64 architecture
Summary: This is consistent with the integrated assembler. All mips64 codegen tests previously passed -mcpu. Removed -mcpu from blez_bgez.ll and const-mult.ll to cover the default case. Ideally, the two implementations of selectMipsCPU() will be merged but it's proven difficult to find a home for the function that doesn't cause link errors. For now, we'll hoist the common functionality into a function and mark it with FIXME's. Reviewers: jacksprat, matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D2830 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201782 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp24
-rw-r--r--lib/Target/Mips/MipsSubtarget.cpp17
2 files changed, 30 insertions, 11 deletions
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
index e6b4e383e3..637b668f67 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
@@ -39,6 +39,20 @@
using namespace llvm;
+/// Select the Mips CPU for the given triple and cpu name.
+/// FIXME: Merge with the copy in MipsSubtarget.cpp
+static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) {
+ if (CPU.empty()) {
+ Triple TheTriple(TT);
+ if (TheTriple.getArch() == Triple::mips ||
+ TheTriple.getArch() == Triple::mipsel)
+ CPU = "mips32";
+ else
+ CPU = "mips64";
+ }
+ return CPU;
+}
+
static MCInstrInfo *createMipsMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMipsMCInstrInfo(X);
@@ -53,15 +67,7 @@ static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
- if (CPU.empty()) {
- Triple TheTriple(TT);
- // FIXME: CodeGen picks mips32 in both cases.
- if (TheTriple.getArch() == Triple::mips ||
- TheTriple.getArch() == Triple::mipsel)
- CPU = "mips32";
- else
- CPU = "mips64";
- }
+ CPU = selectMipsCPU(TT, CPU);
MCSubtargetInfo *X = new MCSubtargetInfo();
InitMipsMCSubtargetInfo(X, TT, CPU, FS);
return X;
diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp
index a715b6285c..a5d910e3e5 100644
--- a/lib/Target/Mips/MipsSubtarget.cpp
+++ b/lib/Target/Mips/MipsSubtarget.cpp
@@ -59,6 +59,20 @@ Mips16ConstantIslands(
cl::desc("MIPS: mips16 constant islands enable."),
cl::init(true));
+/// Select the Mips CPU for the given triple and cpu name.
+/// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
+static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) {
+ if (CPU.empty()) {
+ Triple TheTriple(TT);
+ if (TheTriple.getArch() == Triple::mips ||
+ TheTriple.getArch() == Triple::mipsel)
+ CPU = "mips32";
+ else
+ CPU = "mips64";
+ }
+ return CPU;
+}
+
void MipsSubtarget::anchor() { }
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
@@ -75,8 +89,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT)
{
std::string CPUName = CPU;
- if (CPUName.empty())
- CPUName = "mips32";
+ CPUName = selectMipsCPU(TT, CPUName);
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);