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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-13 13:08:38 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-13 13:08:38 +0000 |
| commit | ef8e5671375cde78dd9589ca21ffd34932acacd6 (patch) | |
| tree | 18c21d0dc6edf5df80ffef3723e158a924b59c49 /lib/Target/Mips | |
| parent | 21ed78f564ff3750690204c78cb870f95104ea58 (diff) | |
| download | llvm-ef8e5671375cde78dd9589ca21ffd34932acacd6.tar.gz llvm-ef8e5671375cde78dd9589ca21ffd34932acacd6.tar.bz2 llvm-ef8e5671375cde78dd9589ca21ffd34932acacd6.tar.xz | |
[mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6
Summary:
These MIPS-3D instructions have never been implemented in LLVM so we only
add testcases.
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4115
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210899 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
| -rw-r--r-- | lib/Target/Mips/Mips32r6InstrInfo.td | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index 2ed580e67a..f242141815 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -25,7 +25,6 @@ include "Mips32r6InstrFormats.td" // Reencoded: sdbbp // Reencoded: sdc2 // Reencoded: swc2 -// Removed: bc1any2, bc1any4 // Rencoded: [ls][wd]c2 def brtarget21 : Operand<OtherVT> { |