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author | Che-Liang Chiou <clchiou@gmail.com> | 2011-03-02 03:20:28 +0000 |
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committer | Che-Liang Chiou <clchiou@gmail.com> | 2011-03-02 03:20:28 +0000 |
commit | fd8978b021dbb0b9b09084dcc707c2054ff76280 (patch) | |
tree | cdbd6a22e3787047cdb1edcaa79065a2231b6a9c /lib/Target/PTX/PTXISelLowering.cpp | |
parent | 9ff5de99df4820a128e525e077333047cfe50661 (diff) | |
download | llvm-fd8978b021dbb0b9b09084dcc707c2054ff76280.tar.gz llvm-fd8978b021dbb0b9b09084dcc707c2054ff76280.tar.bz2 llvm-fd8978b021dbb0b9b09084dcc707c2054ff76280.tar.xz |
Extend initial support for primitive types in PTX backend
- Allow i16, i32, i64, float, and double types, using the native .u16,
.u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.
Patch by Justin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PTX/PTXISelLowering.cpp')
-rw-r--r-- | lib/Target/PTX/PTXISelLowering.cpp | 31 |
1 files changed, 24 insertions, 7 deletions
diff --git a/lib/Target/PTX/PTXISelLowering.cpp b/lib/Target/PTX/PTXISelLowering.cpp index d30c9ecbe4..147b2a82cf 100644 --- a/lib/Target/PTX/PTXISelLowering.cpp +++ b/lib/Target/PTX/PTXISelLowering.cpp @@ -20,6 +20,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -27,13 +28,17 @@ PTXTargetLowering::PTXTargetLowering(TargetMachine &TM) : TargetLowering(TM, new TargetLoweringObjectFileELF()) { // Set up the register classes. addRegisterClass(MVT::i1, PTX::PredsRegisterClass); - addRegisterClass(MVT::i32, PTX::RRegs32RegisterClass); + addRegisterClass(MVT::i16, PTX::RRegu16RegisterClass); + addRegisterClass(MVT::i32, PTX::RRegu32RegisterClass); + addRegisterClass(MVT::i64, PTX::RRegu64RegisterClass); addRegisterClass(MVT::f32, PTX::RRegf32RegisterClass); - + addRegisterClass(MVT::f64, PTX::RRegf64RegisterClass); + setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); setOperationAction(ISD::ConstantFP, MVT::f32, Legal); - + setOperationAction(ISD::ConstantFP, MVT::f64, Legal); + // Customize translation of memory addresses setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); @@ -90,10 +95,13 @@ struct argmap_entry { bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; } } argmap[] = { argmap_entry(MVT::i1, PTX::PredsRegisterClass), - argmap_entry(MVT::i32, PTX::RRegs32RegisterClass), - argmap_entry(MVT::f32, PTX::RRegf32RegisterClass) + argmap_entry(MVT::i16, PTX::RRegu16RegisterClass), + argmap_entry(MVT::i32, PTX::RRegu32RegisterClass), + argmap_entry(MVT::i64, PTX::RRegu64RegisterClass), + argmap_entry(MVT::f32, PTX::RRegf32RegisterClass), + argmap_entry(MVT::f64, PTX::RRegf64RegisterClass) }; -} // end anonymous namespace +} // end anonymous namespace SDValue PTXTargetLowering:: LowerFormalArguments(SDValue Chain, @@ -192,12 +200,21 @@ SDValue PTXTargetLowering:: SDValue Flag; unsigned reg; - if (Outs[0].VT == MVT::i32) { + if (Outs[0].VT == MVT::i16) { + reg = PTX::RH0; + } + else if (Outs[0].VT == MVT::i32) { reg = PTX::R0; } + else if (Outs[0].VT == MVT::i64) { + reg = PTX::RD0; + } else if (Outs[0].VT == MVT::f32) { reg = PTX::F0; } + else if (Outs[0].VT == MVT::f64) { + reg = PTX::FD0; + } else { assert(false && "Can return only basic types"); } |