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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-24 16:52:04 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-06-24 16:52:04 +0000 |
commit | 2e8bd8950345b0857130dd0f4068222a79c103f2 (patch) | |
tree | 0df0da0a1dc819633ffc41e4eff9c8dd044f9f47 /lib/Target/PowerPC/AsmParser | |
parent | a6a3fd6415f73e2db7ba7556925b0957a29b9801 (diff) | |
download | llvm-2e8bd8950345b0857130dd0f4068222a79c103f2.tar.gz llvm-2e8bd8950345b0857130dd0f4068222a79c103f2.tar.bz2 llvm-2e8bd8950345b0857130dd0f4068222a79c103f2.tar.xz |
[PowerPC] Add predicted forms of branches
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
For these, I've added new PPC::Predicate codes corresponding
to the BO values for predicted branch forms, and updated insn
printing to print them correctly. I've also added new aliases
for the asm parser matching the new forms.
- bt/bf
I've added new aliases matching to gBC etc.
- bd(n)z variants
I've added new instruction patterns for the predicted forms.
In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184754 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/AsmParser')
-rw-r--r-- | lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 999c677824..6803d664bc 100644 --- a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -747,6 +747,22 @@ bool PPCAsmParser:: ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) { // The first operand is the token for the instruction name. + // If the next character is a '+' or '-', we need to add it to the + // instruction name, to match what TableGen is doing. + if (getLexer().is(AsmToken::Plus)) { + getLexer().Lex(); + char *NewOpcode = new char[Name.size() + 1]; + memcpy(NewOpcode, Name.data(), Name.size()); + NewOpcode[Name.size()] = '+'; + Name = StringRef(NewOpcode, Name.size() + 1); + } + if (getLexer().is(AsmToken::Minus)) { + getLexer().Lex(); + char *NewOpcode = new char[Name.size() + 1]; + memcpy(NewOpcode, Name.data(), Name.size()); + NewOpcode[Name.size()] = '-'; + Name = StringRef(NewOpcode, Name.size() + 1); + } // If the instruction ends in a '.', we need to create a separate // token for it, to match what TableGen is doing. size_t Dot = Name.find('.'); |