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| author | Chris Lattner <sabre@nondot.org> | 2006-06-16 17:34:12 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-06-16 17:34:12 +0000 |
| commit | a7a5854f1c3710f4bedf069be4771b81e449f2a3 (patch) | |
| tree | 438c2801d45b3995eed10e57be580d2d2797f172 /lib/Target/PowerPC/PPC.td | |
| parent | 6557f186896b9a4f57ea354ee04e0c74c389e0e1 (diff) | |
| download | llvm-a7a5854f1c3710f4bedf069be4771b81e449f2a3.tar.gz llvm-a7a5854f1c3710f4bedf069be4771b81e449f2a3.tar.bz2 llvm-a7a5854f1c3710f4bedf069be4771b81e449f2a3.tar.xz | |
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC.td')
| -rw-r--r-- | lib/Target/PowerPC/PPC.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index bc4f3e74e8..6d23657512 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -19,10 +19,10 @@ include "../Target.td" // PowerPC Subtarget features. // -def Feature64Bit : SubtargetFeature<"64bit","Is64Bit", "true", +def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", "Enable 64-bit instructions">; -def Feature64BitRegs : SubtargetFeature<"64bitregs","Has64BitRegs", "true", - "Enable 64-bit registers [beta]">; +def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", + "Enable 64-bit registers usage for ppc32 [beta]">; def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", "Enable Altivec instructions">; def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true", |