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authorChris Lattner <sabre@nondot.org>2005-10-23 05:28:51 +0000
committerChris Lattner <sabre@nondot.org>2005-10-23 05:28:51 +0000
commit2e1f823aed93249afba72e46ce8a2997bd2b97cf (patch)
treee8cde2c0fb0940d3a9be226c635b0660656905d3 /lib/Target/PowerPC/PPC.td
parent54195c1a9d8ac23d2dc1dfca818384cd26abe19b (diff)
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improve -help output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23892 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC.td')
-rw-r--r--lib/Target/PowerPC/PPC.td10
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index d6a26766a8..166a98fc13 100644
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -30,15 +30,15 @@ include "PPCInstrInfo.td"
//
def Feature64Bit : SubtargetFeature<"64bit",
- "Should 64 bit instructions be used">;
+ "Enable 64-bit instructions">;
def Feature64BitRegs : SubtargetFeature<"64bitregs",
- "Should 64 bit registers be used">;
+ "Enable 64-bit registers">;
def FeatureAltivec : SubtargetFeature<"altivec",
- "Should Altivec instructions be used">;
+ "Enable Altivec instructions">;
def FeatureGPUL : SubtargetFeature<"gpul",
- "Should GPUL instructions be used">;
+ "Enable GPUL instructions">;
def FeatureFSqrt : SubtargetFeature<"fsqrt",
- "Should the fsqrt instruction be used">;
+ "Enable the fsqrt instruction">;
//===----------------------------------------------------------------------===//
// PowerPC chips sets supported.