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| author | Jim Laskey <jlaskey@mac.com> | 2005-10-19 19:51:16 +0000 |
|---|---|---|
| committer | Jim Laskey <jlaskey@mac.com> | 2005-10-19 19:51:16 +0000 |
| commit | 538421411a4a0a070bbd789e88657689ca504dbe (patch) | |
| tree | e82291119677cb6e787ec7acf45238d06297cc47 /lib/Target/PowerPC/PPC.td | |
| parent | 3d925442619eabbca9ac7d0ac2e25ee79c01c31c (diff) | |
| download | llvm-538421411a4a0a070bbd789e88657689ca504dbe.tar.gz llvm-538421411a4a0a070bbd789e88657689ca504dbe.tar.bz2 llvm-538421411a4a0a070bbd789e88657689ca504dbe.tar.xz | |
Added InstrSchedClass to each of the PowerPC Instructions.
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC.td')
| -rw-r--r-- | lib/Target/PowerPC/PPC.td | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 4798ae8d17..36dc1641d7 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -20,8 +20,45 @@ include "../Target.td" //===----------------------------------------------------------------------===// include "PPCRegisterInfo.td" +include "PPCSchedule.td" include "PPCInstrInfo.td" + + +//===----------------------------------------------------------------------===// +// PowerPC Subtarget features. +// + +def F64Bit : SubtargetFeature<"64bit", + "Should 64 bit instructions be used">; +def F64BitRegs : SubtargetFeature<"64bitregs", + "Should 64 bit registers be used">; +def FAltivec : SubtargetFeature<"altivec", + "Should Altivec instructions be used">; +def FGPUL : SubtargetFeature<"gpul", + "Should GPUL instructions be used">; +def FFSQRT : SubtargetFeature<"fsqrt", + "Should the fsqrt instruction be used">; + +//===----------------------------------------------------------------------===// +// PowerPC chips sets supported +// + +def : Processor<"601", G3Itineraries, []>; +def : Processor<"602", G3Itineraries, []>; +def : Processor<"603", G3Itineraries, []>; +def : Processor<"604", G3Itineraries, []>; +def : Processor<"750", G3Itineraries, []>; +def : Processor<"7400", G4Itineraries, [FAltivec]>; +def : Processor<"g4", G4Itineraries, [FAltivec]>; +def : Processor<"7450", G4PlusItineraries, [FAltivec]>; +def : Processor<"g4+", G4PlusItineraries, [FAltivec]>; +def : Processor<"970", G5Itineraries, + [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>; +def : Processor<"g5", G5Itineraries, + [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>; + + def PPC : Target { // Pointers on PPC are 32-bits in size. let PointerType = i32; |