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| author | Jim Laskey <jlaskey@mac.com> | 2005-10-21 19:05:19 +0000 |
|---|---|---|
| committer | Jim Laskey <jlaskey@mac.com> | 2005-10-21 19:05:19 +0000 |
| commit | f5fc2cbd6bcf80cc34c8114007f31d8ffd1d138d (patch) | |
| tree | 2ac16282f3999fb8ceb632ffcbff4a5ad12570e6 /lib/Target/PowerPC/PPC.td | |
| parent | 4bb9cbb73075c350eadaf51d2dab8403764c9a60 (diff) | |
| download | llvm-f5fc2cbd6bcf80cc34c8114007f31d8ffd1d138d.tar.gz llvm-f5fc2cbd6bcf80cc34c8114007f31d8ffd1d138d.tar.bz2 llvm-f5fc2cbd6bcf80cc34c8114007f31d8ffd1d138d.tar.xz | |
Plugin new subtarget backend into the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23870 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC.td')
| -rw-r--r-- | lib/Target/PowerPC/PPC.td | 43 |
1 files changed, 25 insertions, 18 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 36dc1641d7..cfe2b5f8ed 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -26,37 +26,44 @@ include "PPCInstrInfo.td" //===----------------------------------------------------------------------===// -// PowerPC Subtarget features. +// PowerPC Subtarget features (sorted by name). // -def F64Bit : SubtargetFeature<"64bit", - "Should 64 bit instructions be used">; -def F64BitRegs : SubtargetFeature<"64bitregs", - "Should 64 bit registers be used">; -def FAltivec : SubtargetFeature<"altivec", - "Should Altivec instructions be used">; -def FGPUL : SubtargetFeature<"gpul", - "Should GPUL instructions be used">; -def FFSQRT : SubtargetFeature<"fsqrt", - "Should the fsqrt instruction be used">; +def Feature64Bit : SubtargetFeature<"64bit", + "Should 64 bit instructions be used">; +def Feature64BitRegs : SubtargetFeature<"64bitregs", + "Should 64 bit registers be used">; +def FeatureAltivec : SubtargetFeature<"altivec", + "Should Altivec instructions be used">; +def FeatureFSqrt : SubtargetFeature<"fsqrt", + "Should the fsqrt instruction be used">; +def FeatureGPUL : SubtargetFeature<"gpul", + "Should GPUL instructions be used">; //===----------------------------------------------------------------------===// -// PowerPC chips sets supported +// PowerPC chips sets supported (sorted by name) // def : Processor<"601", G3Itineraries, []>; def : Processor<"602", G3Itineraries, []>; def : Processor<"603", G3Itineraries, []>; +def : Processor<"603e", G3Itineraries, []>; +def : Processor<"603ev", G3Itineraries, []>; def : Processor<"604", G3Itineraries, []>; +def : Processor<"604e", G3Itineraries, []>; +def : Processor<"620", G3Itineraries, []>; +def : Processor<"7400", G4Itineraries, [FeatureAltivec]>; +def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>; def : Processor<"750", G3Itineraries, []>; -def : Processor<"7400", G4Itineraries, [FAltivec]>; -def : Processor<"g4", G4Itineraries, [FAltivec]>; -def : Processor<"7450", G4PlusItineraries, [FAltivec]>; -def : Processor<"g4+", G4PlusItineraries, [FAltivec]>; def : Processor<"970", G5Itineraries, - [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>; + [FeatureAltivec, FeatureGPUL, FeatureFSqrt, + Feature64Bit, Feature64BitRegs]>; +def : Processor<"g4", G4Itineraries, [FeatureAltivec]>; +def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>; def : Processor<"g5", G5Itineraries, - [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>; + [FeatureAltivec, FeatureGPUL, FeatureFSqrt, + Feature64Bit, Feature64BitRegs]>; +def : Processor<"generic", G3Itineraries, []>; def PPC : Target { |