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| author | Hal Finkel <hfinkel@anl.gov> | 2014-03-26 16:12:58 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-03-26 16:12:58 +0000 |
| commit | 7363d2223e09fd78094fba652223785f0d63c196 (patch) | |
| tree | 832288b11dc53f379298b32c7aef71cfed503783 /lib/Target/PowerPC/PPCCallingConv.td | |
| parent | 8e7aa4be58277562240e5083a18bd52d6e76abf5 (diff) | |
| download | llvm-7363d2223e09fd78094fba652223785f0d63c196.tar.gz llvm-7363d2223e09fd78094fba652223785f0d63c196.tar.bz2 llvm-7363d2223e09fd78094fba652223785f0d63c196.tar.xz | |
[PowerPC] Add v2i64 as a legal VSX type
v2i64 needs to be a legal VSX type because it is the SetCC result type from
v2f64 comparisons. We need to expand all non-arithmetic v2i64 operations.
This fixes the lowering for v2f64 VSELECT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204828 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCCallingConv.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCCallingConv.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td index 291627a21f..5e3074bacc 100644 --- a/lib/Target/PowerPC/PPCCallingConv.td +++ b/lib/Target/PowerPC/PPCCallingConv.td @@ -36,7 +36,7 @@ def RetCC_PPC : CallingConv<[ CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>, // Vector types are always returned in V2. - CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64], CCAssignToReg<[V2]>> + CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToReg<[V2]>> ]>; @@ -70,7 +70,7 @@ def RetCC_PPC64_ELF_FIS : CallingConv<[ CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, CCIfType<[f32], CCAssignToReg<[F1, F2]>>, CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>, - CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64], CCAssignToReg<[V2]>> + CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToReg<[V2]>> ]>; //===----------------------------------------------------------------------===// @@ -104,7 +104,7 @@ def CC_PPC32_SVR4_Common : CallingConv<[ CCIfType<[f32,f64], CCAssignToStack<8, 8>>, // Vectors get 16-byte stack slots that are 16-byte aligned. - CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64], CCAssignToStack<16, 16>> + CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>> ]>; // This calling convention puts vector arguments always on the stack. It is used @@ -118,7 +118,7 @@ def CC_PPC32_SVR4_VarArg : CallingConv<[ // put vector arguments in vector registers before putting them on the stack. def CC_PPC32_SVR4 : CallingConv<[ // The first 12 Vector arguments are passed in AltiVec registers. - CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64], + CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>, CCDelegateTo<CC_PPC32_SVR4_Common> |